Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan6
OS Platform: LIN64 Target Device: xc6slx45
Project ID (random number) 569837c0f8d448f5be85c6656ddfb0c8.DD1B8F1A9C854E04B347BDEBCA743099.2 Target Package: csg324
Registration ID 177299941_0_0_655 Target Speed: -2
Date Generated 2013-04-09T20:42:04 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 12.04.2 LTS
CPU Name Intel(R) Core(TM) i5 CPU M 520 @ 2.40GHz CPU Speed 1199.000 MHz
OS Name Ubuntu OS Release Ubuntu 12.04.2 LTS
CPU Name Intel(R) Core(TM) i5 CPU M 520 @ 2.40GHz CPU Speed 1199.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=1
  • 6-bit up loadable accumulator=1
Adders/Subtractors=87
  • 10-bit adder=3
  • 11-bit adder=3
  • 11-bit subtractor=2
  • 12-bit adder=3
  • 12-bit subtractor=2
  • 13-bit subtractor=1
  • 14-bit adder=1
  • 14-bit subtractor=2
  • 16-bit adder=4
  • 16-bit addsub=2
  • 16-bit subtractor=5
  • 17-bit subtractor=1
  • 2-bit adder=4
  • 2-bit subtractor=1
  • 27-bit adder=2
  • 28-bit adder=1
  • 28-bit subtractor=1
  • 3-bit adder=5
  • 30-bit adder=1
  • 32-bit adder=2
  • 32-bit subtractor=1
  • 4-bit adder=1
  • 4-bit subtractor=2
  • 5-bit adder=12
  • 5-bit subtractor=4
  • 6-bit adder=3
  • 6-bit subtractor=5
  • 7-bit adder=5
  • 8-bit subtractor=3
  • 9-bit adder=5
Comparators=142
  • 10-bit comparator equal=1
  • 10-bit comparator greater=2
  • 11-bit comparator greater=7
  • 12-bit comparator greater=5
  • 12-bit comparator lessequal=2
  • 13-bit comparator lessequal=1
  • 14-bit comparator greater=1
  • 14-bit comparator lessequal=1
  • 15-bit comparator equal=1
  • 16-bit comparator equal=11
  • 16-bit comparator greater=11
  • 16-bit comparator lessequal=3
  • 19-bit comparator greater=1
  • 2-bit comparator equal=4
  • 2-bit comparator greater=1
  • 25-bit comparator equal=2
  • 28-bit comparator lessequal=1
  • 3-bit comparator greater=2
  • 32-bit comparator greater=2
  • 32-bit comparator lessequal=2
  • 4-bit comparator equal=1
  • 4-bit comparator greater=11
  • 4-bit comparator lessequal=1
  • 5-bit comparator equal=1
  • 5-bit comparator greater=8
  • 5-bit comparator lessequal=8
  • 6-bit comparator equal=2
  • 6-bit comparator greater=2
  • 7-bit comparator equal=1
  • 7-bit comparator greater=3
  • 7-bit comparator lessequal=3
  • 7-bit comparator not equal=1
  • 8-bit comparator equal=13
  • 8-bit comparator greater=9
  • 8-bit comparator lessequal=2
  • 8-bit comparator not equal=15
Counters=59
  • 10-bit down counter=1
  • 11-bit up counter=2
  • 12-bit down counter=1
  • 12-bit up counter=1
  • 13-bit up counter=1
  • 16-bit down counter=1
  • 16-bit up counter=13
  • 17-bit up counter=1
  • 19-bit up counter=1
  • 2-bit up counter=3
  • 3-bit down counter=3
  • 3-bit up counter=4
  • 30-bit up counter=2
  • 4-bit up counter=11
  • 5-bit down counter=1
  • 5-bit up counter=2
  • 5-bit updown counter=4
  • 6-bit up counter=2
  • 8-bit down counter=2
  • 8-bit up counter=2
  • 8-bit updown counter=1
FSMs=13 Multiplexers=1573
  • 1-bit 16-to-1 multiplexer=8
  • 1-bit 2-to-1 multiplexer=1057
  • 1-bit 3-to-1 multiplexer=3
  • 1-bit 32-to-1 multiplexer=32
  • 1-bit 4-to-1 multiplexer=21
  • 1-bit 5-to-1 multiplexer=5
  • 1-bit 8-to-1 multiplexer=12
  • 10-bit 2-to-1 multiplexer=2
  • 11-bit 2-to-1 multiplexer=8
  • 12-bit 2-to-1 multiplexer=5
  • 128-bit 2-to-1 multiplexer=1
  • 128-bit 4-to-1 multiplexer=1
  • 14-bit 2-to-1 multiplexer=6
  • 16-bit 2-to-1 multiplexer=41
  • 16-bit 3-to-1 multiplexer=1
  • 19-bit 2-to-1 multiplexer=1
  • 2-bit 2-to-1 multiplexer=14
  • 2-bit 4-to-1 multiplexer=2
  • 24-bit 2-to-1 multiplexer=5
  • 27-bit 2-to-1 multiplexer=1
  • 28-bit 2-to-1 multiplexer=1
  • 29-bit 2-to-1 multiplexer=1
  • 3-bit 16-to-1 multiplexer=1
  • 3-bit 2-to-1 multiplexer=25
  • 30-bit 2-to-1 multiplexer=2
  • 32-bit 16-to-1 multiplexer=2
  • 32-bit 2-to-1 multiplexer=70
  • 32-bit 24-to-1 multiplexer=1
  • 32-bit 7-to-1 multiplexer=1
  • 32-bit 8-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=41
  • 48-bit 2-to-1 multiplexer=2
  • 5-bit 2-to-1 multiplexer=56
  • 56-bit 5-to-1 multiplexer=1
  • 6-bit 2-to-1 multiplexer=13
  • 7-bit 2-to-1 multiplexer=10
  • 8-bit 2-to-1 multiplexer=114
  • 8-bit 4-to-1 multiplexer=4
  • 9-bit 2-to-1 multiplexer=1
Multipliers=1
  • 16x16-bit multiplier=1
RAMs=14
  • 16x12-bit single-port distributed Read Only RAM=1
  • 16x8-bit dual-port distributed RAM=2
  • 16x8-bit single-port distributed Read Only RAM=1
  • 256x8-bit single-port block RAM=4
  • 4x2-bit single-port distributed Read Only RAM=1
  • 4x4-bit single-port distributed Read Only RAM=1
  • 4x5-bit single-port distributed Read Only RAM=1
  • 4x6-bit single-port distributed Read Only RAM=1
  • 4x8-bit dual-port distributed RAM=2
Registers=9866
  • Flip-Flops=9866
Xors=193
  • 1-bit xor2=131
  • 1-bit xor3=10
  • 1-bit xor4=3
  • 1-bit xor5=1
  • 1-bit xor6=1
  • 1-bit xor7=1
  • 1-bit xor8=1
  • 1-bit xor9=1
  • 32-bit xor2=40
  • 4-bit xor2=3
  • 8-bit xor2=1
MiscellaneousStatistics
  • AGG_BONDED_IO=134
  • AGG_IO=134
  • AGG_LOCED_IO=134
  • AGG_SLICE=2820
  • NUM_BONDED_IOB=134
  • NUM_BSFULL=5819
  • NUM_BSLUTONLY=2573
  • NUM_BSREGONLY=1615
  • NUM_BSUSED=10007
  • NUM_BUFG=8
  • NUM_BUFGMUX=2
  • NUM_BUFIO2=2
  • NUM_BUFIO2FB=1
  • NUM_BUFPLL_MCB=1
  • NUM_DCM=1
  • NUM_DPRAM_O5ANDO6=32
  • NUM_DSP48A1=3
  • NUM_ILOGIC2=42
  • NUM_IOB_FF=42
  • NUM_IODRP2=2
  • NUM_IODRP2_MCB=22
  • NUM_LOCED_DSP48A1=2
  • NUM_LOCED_IOB=134
  • NUM_LOCED_SLICEL=11
  • NUM_LOCED_SLICEM=19
  • NUM_LOCED_SLICEX=20
  • NUM_LOGIC_O5ANDO6=1915
  • NUM_LOGIC_O5ONLY=374
  • NUM_LOGIC_O6ONLY=5310
  • NUM_LUT_RT_DRIVES_CARRY4=20
  • NUM_LUT_RT_DRIVES_FLOP=604
  • NUM_LUT_RT_EXO5=604
  • NUM_LUT_RT_EXO6=20
  • NUM_LUT_RT_O5=154
  • NUM_LUT_RT_O6=306
  • NUM_MCB=1
  • NUM_OSERDES2=45
  • NUM_PLL_ADV=2
  • NUM_RAMB16BWER=30
  • NUM_RAMB8BWER=2
  • NUM_SLICEL=446
  • NUM_SLICEM=64
  • NUM_SLICEX=2310
  • NUM_SLICE_CARRY4=272
  • NUM_SLICE_CONTROLSET=361
  • NUM_SLICE_CYINIT=10999
  • NUM_SLICE_F7MUX=245
  • NUM_SLICE_F8MUX=67
  • NUM_SLICE_FF=9051
  • NUM_SLICE_LATCHLOGIC=13
  • NUM_SLICE_UNUSEDCTRL=402
  • NUM_SRL_O5ANDO6=131
  • NUM_SRL_O6ONLY=6
  • NUM_UNUSABLE_FF_BELS=753
  • Xilinx Core mig_v3_6_ddr2_s6, Coregen 12.3=1
NetStatistics
  • NumNets_Active=14414
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=627
  • NumNodesOfType_Active_BOUNCEIN=2020
  • NumNodesOfType_Active_BUFGOUT=10
  • NumNodesOfType_Active_BUFHINP2OUT=41
  • NumNodesOfType_Active_BUFIOINP=3
  • NumNodesOfType_Active_CLKPIN=2509
  • NumNodesOfType_Active_CLKPINFEED=95
  • NumNodesOfType_Active_CNTRLPIN=3102
  • NumNodesOfType_Active_DOUBLE=22786
  • NumNodesOfType_Active_GENERIC=306
  • NumNodesOfType_Active_GENERIC1=23
  • NumNodesOfType_Active_GLOBAL=534
  • NumNodesOfType_Active_INPUT=1633
  • NumNodesOfType_Active_IOBIN2OUT=241
  • NumNodesOfType_Active_IOBINPUT=131
  • NumNodesOfType_Active_IOBOUTPUT=331
  • NumNodesOfType_Active_LUTINPUT=36636
  • NumNodesOfType_Active_OUTBOUND=14400
  • NumNodesOfType_Active_OUTPUT=14242
  • NumNodesOfType_Active_PADINPUT=120
  • NumNodesOfType_Active_PADOUTPUT=77
  • NumNodesOfType_Active_PINBOUNCE=10342
  • NumNodesOfType_Active_PINFEED=41865
  • NumNodesOfType_Active_PINFEED1=32
  • NumNodesOfType_Active_PINFEED2=144
  • NumNodesOfType_Active_QUAD=12511
  • NumNodesOfType_Active_REGINPUT=3889
  • NumNodesOfType_Active_SINGLE=27874
  • NumNodesOfType_Gnd_BOUNCEACROSS=9
  • NumNodesOfType_Gnd_BOUNCEIN=396
  • NumNodesOfType_Gnd_CLKPIN=3
  • NumNodesOfType_Gnd_CNTRLPIN=72
  • NumNodesOfType_Gnd_DOUBLE=70
  • NumNodesOfType_Gnd_GENERIC=5
  • NumNodesOfType_Gnd_HGNDOUT=203
  • NumNodesOfType_Gnd_INPUT=1263
  • NumNodesOfType_Gnd_IOBIN2OUT=32
  • NumNodesOfType_Gnd_IOBINPUT=205
  • NumNodesOfType_Gnd_IOBOUTPUT=5
  • NumNodesOfType_Gnd_LUTINPUT=448
  • NumNodesOfType_Gnd_OUTBOUND=81
  • NumNodesOfType_Gnd_OUTPUT=97
  • NumNodesOfType_Gnd_PADINPUT=5
  • NumNodesOfType_Gnd_PINBOUNCE=532
  • NumNodesOfType_Gnd_PINFEED=2012
  • NumNodesOfType_Gnd_QUAD=1
  • NumNodesOfType_Gnd_REGINPUT=86
  • NumNodesOfType_Gnd_SINGLE=147
  • NumNodesOfType_Vcc_CLKPIN=5
  • NumNodesOfType_Vcc_CNTRLPIN=164
  • NumNodesOfType_Vcc_HVCCOUT=939
  • NumNodesOfType_Vcc_INPUT=65
  • NumNodesOfType_Vcc_IOBIN2OUT=2
  • NumNodesOfType_Vcc_IOBINPUT=4
  • NumNodesOfType_Vcc_KVCCOUT=103
  • NumNodesOfType_Vcc_LUTINPUT=2845
  • NumNodesOfType_Vcc_PINBOUNCE=116
  • NumNodesOfType_Vcc_PINFEED=3026
  • NumNodesOfType_Vcc_REGINPUT=57
SiteStatistics
  • BUFG-BUFGMUX=8
  • IOB-IOBM=71
  • IOB-IOBS=63
  • IODRP2-IODELAY2=2
  • IODRP2_MCB-IODELAY2=22
  • OSERDES2-OLOGIC2=45
  • SLICEL-SLICEM=209
  • SLICEX-SLICEL=553
  • SLICEX-SLICEM=403
SiteSummary
  • BUFG=8
  • BUFGMUX=2
  • BUFGMUX_BUFGMUX=2
  • BUFG_BUFG=8
  • BUFIO2=2
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=2
  • BUFPLL_MCB=1
  • BUFPLL_MCB_BUFPLL_MCB=1
  • CARRY4=272
  • DCM=1
  • DCM_DCM=1
  • DSP48A1=3
  • DSP48A1_DSP48A1=3
  • FF_SR=1701
  • HARD0=71
  • HARD1=40
  • ILOGIC2=42
  • ILOGIC2_IFF=42
  • INVERTER=2
  • IOB=134
  • IOB_IMUX=80
  • IOB_INBUF=80
  • IOB_OUTBUF=75
  • IODRP2=2
  • IODRP2_IODRP2=2
  • IODRP2_MCB=22
  • IODRP2_MCB_IODRP2_MCB=22
  • LUT5=3023
  • LUT6=7515
  • LUT_OR_MEM5=187
  • LUT_OR_MEM6=205
  • MCB=1
  • MCB_MCB=1
  • NULLMUX=2
  • OSERDES2=45
  • OSERDES2_OSERDES2=45
  • PAD=134
  • PLL_ADV=2
  • PLL_ADV_PLL_ADV=2
  • PULL_OR_KEEP1=39
  • RAMB16BWER=30
  • RAMB16BWER_RAMB16BWER=30
  • RAMB8BWER=2
  • RAMB8BWER_RAMB8BWER=2
  • REG_SR=7363
  • SELMUX2_1=386
  • SLICEL=446
  • SLICEM=64
  • SLICEX=2310
 
Configuration Data
BUFGMUX
  • S=[S_INV:0] [S:2]
BUFGMUX_BUFGMUX
  • CLK_SEL_TYPE=[SYNC:2]
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:0] [S:2]
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:2]
  • DIVIDE_BYPASS=[TRUE:2]
  • I_INVERT=[FALSE:2]
BUFPLL_MCB_BUFPLL_MCB
  • DIVIDE=[2:1]
  • LOCK_SRC=[LOCK_TO_0:1]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
DSP48A1
  • CEA=[CEA_INV:0] [CEA:3]
  • CEB=[CEB_INV:0] [CEB:3]
  • CEC=[CEC:3] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:3]
  • CED=[CED_INV:0] [CED:3]
  • CEM=[CEM_INV:0] [CEM:3]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:3]
  • CEP=[CEP:3] [CEP_INV:0]
  • CLK=[CLK:3] [CLK_INV:0]
  • RSTA=[RSTA:3] [RSTA_INV:0]
  • RSTB=[RSTB:3] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:3]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:3]
  • RSTD=[RSTD_INV:0] [RSTD:3]
  • RSTM=[RSTM:3] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:3]
  • RSTP=[RSTP_INV:0] [RSTP:3]
DSP48A1_DSP48A1
  • A0REG=[0:3]
  • A1REG=[0:1] [1:2]
  • B0REG=[0:3]
  • B1REG=[0:1] [1:2]
  • B_INPUT=[DIRECT:3]
  • CARRYINREG=[0:1] [1:2]
  • CARRYINSEL=[OPMODE5:3]
  • CARRYOUTREG=[0:1] [1:2]
  • CEA=[CEA_INV:0] [CEA:3]
  • CEB=[CEB_INV:0] [CEB:3]
  • CEC=[CEC:3] [CEC_INV:0]
  • CECARRYIN=[CECARRYIN_INV:0] [CECARRYIN:3]
  • CED=[CED_INV:0] [CED:3]
  • CEM=[CEM_INV:0] [CEM:3]
  • CEOPMODE=[CEOPMODE_INV:0] [CEOPMODE:3]
  • CEP=[CEP:3] [CEP_INV:0]
  • CLK=[CLK:3] [CLK_INV:0]
  • CREG=[0:1] [1:2]
  • DREG=[0:1] [1:2]
  • MREG=[0:1] [1:2]
  • OPMODEREG=[0:3]
  • PREG=[0:1] [1:2]
  • RSTA=[RSTA:3] [RSTA_INV:0]
  • RSTB=[RSTB:3] [RSTB_INV:0]
  • RSTC=[RSTC_INV:0] [RSTC:3]
  • RSTCARRYIN=[RSTCARRYIN_INV:0] [RSTCARRYIN:3]
  • RSTD=[RSTD_INV:0] [RSTD:3]
  • RSTM=[RSTM:3] [RSTM_INV:0]
  • RSTOPMODE=[RSTOPMODE_INV:0] [RSTOPMODE:3]
  • RSTP=[RSTP_INV:0] [RSTP:3]
  • RSTTYPE=[SYNC:3]
FF_SR
  • CK=[CK:1701] [CK_INV:0]
  • SRINIT=[SRINIT0:1673] [SRINIT1:28]
  • SYNC_ATTR=[ASYNC:1435] [SYNC:266]
ILOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:42]
  • CLK1=[CLK1:32] [CLK1_INV:0]
ILOGIC2_IFF
  • CLK0=[CLK0_INV:0] [CLK0:42]
  • CLK1=[CLK1:32] [CLK1_INV:0]
  • DDR_ALIGNMENT=[C0:32]
  • IFFTYPE=[FF:10] [DDR:32]
  • SAME_EDGE_PIPELINED=[FALSE:32]
  • SRINIT_Q=[0:41] [1:1]
  • SRTYPE_Q=[ASYNC:9] [SYNC:33]
IOB_INBUF
  • IN_TERM=[NONE:18]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:28]
  • SLEW=[SLOW:28]
  • SUSPEND=[3STATE:75]
IODRP2
  • IOCLK0=[IOCLK0_INV:0] [IOCLK0:2]
IODRP2_IODRP2
  • COUNTER_WRAPAROUND=[WRAPAROUND:2]
  • DATA_RATE=[SDR:2]
  • DELAYCHAIN_OSC=[FALSE:2]
  • DELAY_SRC=[IO:2]
  • IDELAY_MODE=[NORMAL:2]
  • IDELAY_TYPE=[DEFAULT:2]
  • IOCLK0=[IOCLK0_INV:0] [IOCLK0:2]
  • IODELAY_CHANGE=[CHANGE_ON_DATA:2]
  • SERDES_MODE=[NONE:2]
  • TEST_GLITCH_FILTER=[FALSE:2]
IODRP2_MCB
  • IOCLK0=[IOCLK0_INV:0] [IOCLK0:22]
IODRP2_MCB_IODRP2_MCB
  • DATA_RATE=[SDR:22]
  • IOCLK0=[IOCLK0_INV:0] [IOCLK0:22]
  • SERDES_MODE=[SLAVE:11] [MASTER:11]
LUT_OR_MEM5
  • CLK=[CLK:163] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:24] [RAM:163]
  • RAMMODE=[SRL16:131] [DPRAM32:32]
LUT_OR_MEM6
  • CLK=[CLK:169] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:36] [RAM:169]
  • RAMMODE=[SRL16:137] [DPRAM32:32]
MCB
  • P0CMDCLK=[P0CMDCLK:1] [P0CMDCLK_INV:0]
  • P0CMDEN=[P0CMDEN:1] [P0CMDEN_INV:0]
  • P0RDCLK=[P0RDCLK:1] [P0RDCLK_INV:0]
  • P0RDEN=[P0RDEN_INV:0] [P0RDEN:1]
  • P0WRCLK=[P0WRCLK_INV:0] [P0WRCLK:1]
  • P0WREN=[P0WREN_INV:0] [P0WREN:1]
  • P1CMDCLK=[P1CMDCLK:1] [P1CMDCLK_INV:0]
  • P1CMDEN=[P1CMDEN_INV:0] [P1CMDEN:1]
  • P1RDCLK=[P1RDCLK_INV:0] [P1RDCLK:1]
  • P1RDEN=[P1RDEN:1] [P1RDEN_INV:0]
  • P1WRCLK=[P1WRCLK_INV:0] [P1WRCLK:1]
  • P1WREN=[P1WREN:1] [P1WREN_INV:0]
  • P2CLK=[P2CLK:1] [P2CLK_INV:0]
  • P2CMDCLK=[P2CMDCLK_INV:0] [P2CMDCLK:1]
  • P2CMDEN=[P2CMDEN:1] [P2CMDEN_INV:0]
  • P2EN=[P2EN:1] [P2EN_INV:0]
  • P3CLK=[P3CLK:1] [P3CLK_INV:0]
  • P3CMDCLK=[P3CMDCLK_INV:0] [P3CMDCLK:1]
  • P3CMDEN=[P3CMDEN_INV:0] [P3CMDEN:1]
  • P3EN=[P3EN_INV:0] [P3EN:1]
  • P4CLK=[P4CLK_INV:0] [P4CLK:1]
  • P4CMDCLK=[P4CMDCLK_INV:0] [P4CMDCLK:1]
  • P4CMDEN=[P4CMDEN_INV:0] [P4CMDEN:1]
  • P4EN=[P4EN_INV:0] [P4EN:1]
  • P5CLK=[P5CLK_INV:0] [P5CLK:1]
  • P5CMDCLK=[P5CMDCLK_INV:0] [P5CMDCLK:1]
  • P5CMDEN=[P5CMDEN:1] [P5CMDEN_INV:0]
  • P5EN=[P5EN_INV:0] [P5EN:1]
MCB_MCB
  • ARB_NUM_TIME_SLOTS=[12:1]
  • CAL_BYPASS=[NO:1]
  • CAL_CALIBRATION_MODE=[NOCALIBRATION:1]
  • CAL_CLK_DIV=[1:1]
  • CAL_DELAY=[HALF:1]
  • MEM_ADDR_ORDER=[ROW_BANK_COLUMN:1]
  • MEM_BA_SIZE=[3:1]
  • MEM_BURST_LEN=[4:1]
  • MEM_CAS_LATENCY=[5:1]
  • MEM_CA_SIZE=[10:1]
  • MEM_DDR1_2_ODS=[FULL:1]
  • MEM_DDR2_3_HIGH_TEMP_SR=[NORMAL:1]
  • MEM_DDR2_3_PA_SR=[FULL:1]
  • MEM_DDR2_ADD_LATENCY=[0:1]
  • MEM_DDR2_DIFF_DQS_EN=[YES:1]
  • MEM_DDR2_RTT=[50OHMS:1]
  • MEM_DDR2_WRT_RECOVERY=[5:1]
  • MEM_DDR3_ADD_LATENCY=[OFF:1]
  • MEM_DDR3_AUTO_SR=[ENABLED:1]
  • MEM_DDR3_CAS_LATENCY=[6:1]
  • MEM_DDR3_CAS_WR_LATENCY=[5:1]
  • MEM_DDR3_DYN_WRT_ODT=[OFF:1]
  • MEM_DDR3_ODS=[DIV6:1]
  • MEM_DDR3_RTT=[DIV2:1]
  • MEM_DDR3_WRT_RECOVERY=[5:1]
  • MEM_MDDR_ODS=[FULL:1]
  • MEM_MOBILE_PA_SR=[FULL:1]
  • MEM_MOBILE_TC_SR=[0:1]
  • MEM_RAS_VAL=[14:1]
  • MEM_RA_SIZE=[13:1]
  • MEM_RCD_VAL=[4:1]
  • MEM_RTP_VAL=[3:1]
  • MEM_TYPE=[DDR2:1]
  • MEM_WIDTH=[16:1]
  • MEM_WR_VAL=[5:1]
  • MEM_WTR_VAL=[3:1]
  • P0CMDCLK=[P0CMDCLK:1] [P0CMDCLK_INV:0]
  • P0CMDEN=[P0CMDEN:1] [P0CMDEN_INV:0]
  • P0RDCLK=[P0RDCLK:1] [P0RDCLK_INV:0]
  • P0RDEN=[P0RDEN_INV:0] [P0RDEN:1]
  • P0WRCLK=[P0WRCLK_INV:0] [P0WRCLK:1]
  • P0WREN=[P0WREN_INV:0] [P0WREN:1]
  • P1CMDCLK=[P1CMDCLK:1] [P1CMDCLK_INV:0]
  • P1CMDEN=[P1CMDEN_INV:0] [P1CMDEN:1]
  • P1RDCLK=[P1RDCLK_INV:0] [P1RDCLK:1]
  • P1RDEN=[P1RDEN:1] [P1RDEN_INV:0]
  • P1WRCLK=[P1WRCLK_INV:0] [P1WRCLK:1]
  • P1WREN=[P1WREN:1] [P1WREN_INV:0]
  • P2CLK=[P2CLK:1] [P2CLK_INV:0]
  • P2CMDCLK=[P2CMDCLK_INV:0] [P2CMDCLK:1]
  • P2CMDEN=[P2CMDEN:1] [P2CMDEN_INV:0]
  • P2EN=[P2EN:1] [P2EN_INV:0]
  • P3CLK=[P3CLK:1] [P3CLK_INV:0]
  • P3CMDCLK=[P3CMDCLK_INV:0] [P3CMDCLK:1]
  • P3CMDEN=[P3CMDEN_INV:0] [P3CMDEN:1]
  • P3EN=[P3EN_INV:0] [P3EN:1]
  • P4CLK=[P4CLK_INV:0] [P4CLK:1]
  • P4CMDCLK=[P4CMDCLK_INV:0] [P4CMDCLK:1]
  • P4CMDEN=[P4CMDEN_INV:0] [P4CMDEN:1]
  • P4EN=[P4EN_INV:0] [P4EN:1]
  • P5CLK=[P5CLK_INV:0] [P5CLK:1]
  • P5CMDCLK=[P5CMDCLK_INV:0] [P5CMDCLK:1]
  • P5CMDEN=[P5CMDEN:1] [P5CMDEN_INV:0]
  • P5EN=[P5EN_INV:0] [P5EN:1]
  • PORT_CONFIG=[B32_B32_R32_R32_R32_R32:1]
OSERDES2
  • CLK0=[CLK0_INV:0] [CLK0:45]
OSERDES2_OSERDES2
  • BYPASS_GCLK_FF=[TRUE:45]
  • CLK0=[CLK0_INV:0] [CLK0:45]
  • DATA_RATE_OQ=[SDR:45]
  • DATA_RATE_OT=[SDR:45]
  • DATA_WIDTH=[2:45]
  • OUTPUT_MODE=[SINGLE_ENDED:44] [DIFFERENTIAL:1]
  • SERDES_MODE=[SLAVE:3] [MASTER:42]
  • TRAIN_PATTERN=[0:28] [5:16] [15:1]
PLL_ADV
  • RST=[RST:1] [RST_INV:1]
PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:2]
  • CLK_FEEDBACK=[CLKFBOUT:2]
  • COMPENSATION=[INTERNAL:1] [SYSTEM_SYNCHRONOUS:1]
  • PLL_ADD_LEAKAGE=[2:2]
  • PLL_AVDD_COMP_SET=[2:2]
  • PLL_CLAMP_BYPASS=[FALSE:2]
  • PLL_CLAMP_REF_SEL=[1:2]
  • PLL_CLK0MX=[0:2]
  • PLL_CLK1MX=[0:2]
  • PLL_CLK2MX=[0:2]
  • PLL_CLK3MX=[0:2]
  • PLL_CLK4MX=[0:2]
  • PLL_CLK5MX=[0:2]
  • PLL_CLKBURST_CNT=[0:2]
  • PLL_CLKBURST_ENABLE=[TRUE:2]
  • PLL_CLKCNTRL=[0:2]
  • PLL_CLKFBMX=[0:2]
  • PLL_CLKFBOUT2_EDGE=[TRUE:2]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:2]
  • PLL_CLKFBOUT_EDGE=[TRUE:2]
  • PLL_CLKFBOUT_EN=[FALSE:2]
  • PLL_CLKFBOUT_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT0_EDGE=[TRUE:2]
  • PLL_CLKOUT0_EN=[FALSE:2]
  • PLL_CLKOUT0_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT1_EDGE=[TRUE:2]
  • PLL_CLKOUT1_EN=[FALSE:2]
  • PLL_CLKOUT1_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT2_EDGE=[TRUE:2]
  • PLL_CLKOUT2_EN=[FALSE:2]
  • PLL_CLKOUT2_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT3_EDGE=[TRUE:2]
  • PLL_CLKOUT3_EN=[FALSE:2]
  • PLL_CLKOUT3_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT4_EDGE=[TRUE:2]
  • PLL_CLKOUT4_EN=[FALSE:2]
  • PLL_CLKOUT4_NOCOUNT=[TRUE:2]
  • PLL_CLKOUT5_EDGE=[TRUE:2]
  • PLL_CLKOUT5_EN=[FALSE:2]
  • PLL_CLKOUT5_NOCOUNT=[TRUE:2]
  • PLL_CLK_LOST_DETECT=[FALSE:2]
  • PLL_CP=[1:2]
  • PLL_CP_BIAS_TRIP_SHIFT=[TRUE:2]
  • PLL_CP_REPL=[1:2]
  • PLL_CP_RES=[0:2]
  • PLL_DIRECT_PATH_CNTRL=[TRUE:2]
  • PLL_DIVCLK_EDGE=[TRUE:2]
  • PLL_DIVCLK_NOCOUNT=[TRUE:2]
  • PLL_DVDD_COMP_SET=[2:2]
  • PLL_EN=[FALSE:2]
  • PLL_EN_DLY=[TRUE:2]
  • PLL_EN_LEAKAGE=[2:2]
  • PLL_EN_TCLK0=[TRUE:2]
  • PLL_EN_TCLK1=[TRUE:2]
  • PLL_EN_TCLK2=[TRUE:2]
  • PLL_EN_TCLK3=[TRUE:2]
  • PLL_EN_VCO0=[FALSE:2]
  • PLL_EN_VCO1=[FALSE:2]
  • PLL_EN_VCO2=[FALSE:2]
  • PLL_EN_VCO3=[FALSE:2]
  • PLL_EN_VCO4=[FALSE:2]
  • PLL_EN_VCO5=[FALSE:2]
  • PLL_EN_VCO6=[FALSE:2]
  • PLL_EN_VCO7=[FALSE:2]
  • PLL_EN_VCO_DIV1=[FALSE:2]
  • PLL_EN_VCO_DIV6=[TRUE:2]
  • PLL_INTFB=[0:2]
  • PLL_IO_CLKSRC=[0:2]
  • PLL_LFHF=[3:2]
  • PLL_LOCK_FB_DLY=[3:2]
  • PLL_LOCK_REF_DLY=[5:2]
  • PLL_MAN_LF_EN=[TRUE:2]
  • PLL_NBTI_EN=[TRUE:2]
  • PLL_PFD_CNTRL=[8:2]
  • PLL_PFD_DLY=[1:2]
  • PLL_PWRD_CFG=[FALSE:2]
  • PLL_REG_INPUT=[TRUE:2]
  • PLL_RES=[1:2]
  • PLL_SEL_SLIPD=[FALSE:2]
  • PLL_SKEW_CNTRL=[0:2]
  • PLL_TEST_IN_WINDOW=[FALSE:2]
  • PLL_VDD_SEL=[0:2]
  • PLL_VLFHIGH_DIS=[TRUE:2]
  • RST=[RST:1] [RST_INV:1]
PULL_OR_KEEP1
  • PULLTYPE=[PULLUP:4] [PULLDOWN:35]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:30]
  • CLKB=[CLKB_INV:0] [CLKB:14]
  • ENA=[ENA_INV:0] [ENA:30]
  • ENB=[ENB_INV:0] [ENB:14]
  • REGCEA=[REGCEA_INV:0] [REGCEA:6]
  • REGCEB=[REGCEB_INV:0] [REGCEB:6]
  • RSTA=[RSTA:30] [RSTA_INV:0]
  • RSTB=[RSTB:14] [RSTB_INV:0]
  • WEA0=[WEA0:30] [WEA0_INV:0]
  • WEA1=[WEA1:30] [WEA1_INV:0]
  • WEA2=[WEA2:30] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:30]
  • WEB0=[WEB0:14] [WEB0_INV:0]
  • WEB1=[WEB1:14] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:14]
  • WEB3=[WEB3:14] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:30]
  • CLKB=[CLKB_INV:0] [CLKB:14]
  • DATA_WIDTH_A=[1:16] [4:8] [9:2] [18:1] [36:3]
  • DATA_WIDTH_B=[0:16] [4:8] [9:4] [36:2]
  • DOA_REG=[0:30]
  • DOB_REG=[0:30]
  • ENA=[ENA_INV:0] [ENA:30]
  • ENB=[ENB_INV:0] [ENB:14]
  • EN_RSTRAM_A=[TRUE:30]
  • EN_RSTRAM_B=[TRUE:30]
  • RAM_MODE=[TDP:30]
  • REGCEA=[REGCEA_INV:0] [REGCEA:6]
  • REGCEB=[REGCEB_INV:0] [REGCEB:6]
  • RSTA=[RSTA:30] [RSTA_INV:0]
  • RSTB=[RSTB:14] [RSTB_INV:0]
  • RSTTYPE=[SYNC:30]
  • RST_PRIORITY_A=[CE:30]
  • RST_PRIORITY_B=[CE:30]
  • WEA0=[WEA0:30] [WEA0_INV:0]
  • WEA1=[WEA1:30] [WEA1_INV:0]
  • WEA2=[WEA2:30] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:30]
  • WEB0=[WEB0:14] [WEB0_INV:0]
  • WEB1=[WEB1:14] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:14]
  • WEB3=[WEB3:14] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:30]
  • WRITE_MODE_B=[WRITE_FIRST:30]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • DATA_WIDTH_A=[9:2]
  • DATA_WIDTH_B=[9:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • EN_RSTRAM_A=[TRUE:2]
  • EN_RSTRAM_B=[TRUE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
REG_SR
  • CK=[CK:7350] [CK_INV:13]
  • LATCH_OR_FF=[FF:7350] [AND2L:13]
  • SRINIT=[SRINIT0:7202] [SRINIT1:161]
  • SYNC_ATTR=[ASYNC:5758] [SYNC:1605]
SLICEL
  • CLK=[CLK:263] [CLK_INV:5]
SLICEM
  • CLK=[CLK:59] [CLK_INV:0]
SLICEX
  • CLK=[CLK:2086] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=8
  • O=8
BUFGMUX
  • I0=2
  • I1=2
  • O=2
  • S=2
BUFGMUX_BUFGMUX
  • I0=2
  • I1=2
  • O=2
  • S=2
BUFG_BUFG
  • I0=8
  • O=8
BUFIO2
  • DIVCLK=2
  • I=2
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=2
  • I=2
BUFPLL_MCB
  • GCLK=1
  • IOCLK0=1
  • IOCLK1=1
  • LOCK=1
  • LOCKED=1
  • PLLIN0=1
  • PLLIN1=1
  • SERDESSTROBE0=1
  • SERDESSTROBE1=1
BUFPLL_MCB_BUFPLL_MCB
  • GCLK=1
  • IOCLK0=1
  • IOCLK1=1
  • LOCK=1
  • LOCKED=1
  • PLLIN0=1
  • PLLIN1=1
  • SERDESSTROBE0=1
  • SERDESSTROBE1=1
CARRY4
  • CIN=188
  • CO0=2
  • CO1=14
  • CO2=8
  • CO3=189
  • CYINIT=84
  • DI0=268
  • DI1=252
  • DI2=231
  • DI3=189
  • O0=219
  • O1=215
  • O2=202
  • O3=195
  • S0=272
  • S1=266
  • S2=238
  • S3=223
DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
DSP48A1
  • A0=3
  • A1=3
  • A10=3
  • A11=3
  • A12=3
  • A13=3
  • A14=3
  • A15=3
  • A16=3
  • A17=3
  • A2=3
  • A3=3
  • A4=3
  • A5=3
  • A6=3
  • A7=3
  • A8=3
  • A9=3
  • B0=3
  • B1=3
  • B10=3
  • B11=3
  • B12=3
  • B13=3
  • B14=3
  • B15=3
  • B16=3
  • B17=3
  • B2=3
  • B3=3
  • B4=3
  • B5=3
  • B6=3
  • B7=3
  • B8=3
  • B9=3
  • C0=3
  • C1=3
  • C10=3
  • C11=3
  • C12=3
  • C13=3
  • C14=3
  • C15=3
  • C16=3
  • C17=3
  • C18=3
  • C19=3
  • C2=3
  • C20=3
  • C21=3
  • C22=3
  • C23=3
  • C24=3
  • C25=3
  • C26=3
  • C27=3
  • C28=3
  • C29=3
  • C3=3
  • C30=3
  • C31=3
  • C32=3
  • C33=3
  • C34=3
  • C35=3
  • C36=3
  • C37=3
  • C38=3
  • C39=3
  • C4=3
  • C40=3
  • C41=3
  • C42=3
  • C43=3
  • C44=3
  • C45=3
  • C46=3
  • C47=3
  • C5=3
  • C6=3
  • C7=3
  • C8=3
  • C9=3
  • CEA=3
  • CEB=3
  • CEC=3
  • CECARRYIN=3
  • CED=3
  • CEM=3
  • CEOPMODE=3
  • CEP=3
  • CLK=3
  • D0=3
  • D1=3
  • D10=3
  • D11=3
  • D12=3
  • D13=3
  • D14=3
  • D15=3
  • D16=3
  • D17=3
  • D2=3
  • D3=3
  • D4=3
  • D5=3
  • D6=3
  • D7=3
  • D8=3
  • D9=3
  • M10=1
  • M11=1
  • M12=1
  • M13=1
  • M14=1
  • M4=1
  • M5=1
  • M6=1
  • M7=1
  • M8=1
  • M9=1
  • OPMODE0=3
  • OPMODE1=3
  • OPMODE2=3
  • OPMODE3=3
  • OPMODE4=3
  • OPMODE5=3
  • OPMODE6=3
  • OPMODE7=3
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=2
  • P2=2
  • P20=2
  • P21=2
  • P22=2
  • P23=2
  • P24=2
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=3
  • RSTB=3
  • RSTC=3
  • RSTCARRYIN=3
  • RSTD=3
  • RSTM=3
  • RSTOPMODE=3
  • RSTP=3
DSP48A1_DSP48A1
  • A0=3
  • A1=3
  • A10=3
  • A11=3
  • A12=3
  • A13=3
  • A14=3
  • A15=3
  • A16=3
  • A17=3
  • A2=3
  • A3=3
  • A4=3
  • A5=3
  • A6=3
  • A7=3
  • A8=3
  • A9=3
  • B0=3
  • B1=3
  • B10=3
  • B11=3
  • B12=3
  • B13=3
  • B14=3
  • B15=3
  • B16=3
  • B17=3
  • B2=3
  • B3=3
  • B4=3
  • B5=3
  • B6=3
  • B7=3
  • B8=3
  • B9=3
  • C0=3
  • C1=3
  • C10=3
  • C11=3
  • C12=3
  • C13=3
  • C14=3
  • C15=3
  • C16=3
  • C17=3
  • C18=3
  • C19=3
  • C2=3
  • C20=3
  • C21=3
  • C22=3
  • C23=3
  • C24=3
  • C25=3
  • C26=3
  • C27=3
  • C28=3
  • C29=3
  • C3=3
  • C30=3
  • C31=3
  • C32=3
  • C33=3
  • C34=3
  • C35=3
  • C36=3
  • C37=3
  • C38=3
  • C39=3
  • C4=3
  • C40=3
  • C41=3
  • C42=3
  • C43=3
  • C44=3
  • C45=3
  • C46=3
  • C47=3
  • C5=3
  • C6=3
  • C7=3
  • C8=3
  • C9=3
  • CEA=3
  • CEB=3
  • CEC=3
  • CECARRYIN=3
  • CED=3
  • CEM=3
  • CEOPMODE=3
  • CEP=3
  • CLK=3
  • D0=3
  • D1=3
  • D10=3
  • D11=3
  • D12=3
  • D13=3
  • D14=3
  • D15=3
  • D16=3
  • D17=3
  • D2=3
  • D3=3
  • D4=3
  • D5=3
  • D6=3
  • D7=3
  • D8=3
  • D9=3
  • M10=1
  • M11=1
  • M12=1
  • M13=1
  • M14=1
  • M4=1
  • M5=1
  • M6=1
  • M7=1
  • M8=1
  • M9=1
  • OPMODE0=3
  • OPMODE1=3
  • OPMODE2=3
  • OPMODE3=3
  • OPMODE4=3
  • OPMODE5=3
  • OPMODE6=3
  • OPMODE7=3
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=2
  • P2=2
  • P20=2
  • P21=2
  • P22=2
  • P23=2
  • P24=2
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=3
  • RSTB=3
  • RSTC=3
  • RSTCARRYIN=3
  • RSTD=3
  • RSTM=3
  • RSTOPMODE=3
  • RSTP=3
FF_SR
  • CE=762
  • CK=1701
  • D=1701
  • Q=1701
  • SR=554
HARD0
  • 0=71
HARD1
  • 1=40
ILOGIC2
  • CE0=32
  • CLK0=42
  • CLK1=32
  • D=42
  • FABRICOUT=32
  • Q3=32
  • Q4=42
  • SR=42
ILOGIC2_IFF
  • CE0=32
  • CLK0=42
  • CLK1=32
  • D=42
  • Q1=42
  • Q2=32
  • SR=42
INVERTER
  • IN=2
  • OUT=2
IOB
  • DIFFI_IN=2
  • I=80
  • O=75
  • PAD=134
  • PADOUT=2
  • T=48
IOB_IMUX
  • I=78
  • I_B=2
  • OUT=80
IOB_INBUF
  • DIFFI_IN=2
  • OUT=80
  • PAD=80
IOB_OUTBUF
  • IN=75
  • OUT=75
  • TRI=48
IODRP2
  • ADD=2
  • BKST=2
  • CLK=2
  • CS=2
  • DOUT=2
  • IDATAIN=2
  • IOCLK0=2
  • ODATAIN=2
  • SDI=2
  • SDO=2
  • T=2
  • TOUT=2
IODRP2_IODRP2
  • ADD=2
  • BKST=2
  • CLK=2
  • CS=2
  • DOUT=2
  • IDATAIN=2
  • IOCLK0=2
  • ODATAIN=2
  • SDI=2
  • SDO=2
  • T=2
  • TOUT=2
IODRP2_MCB
  • ADD=22
  • AUXADDR0=22
  • AUXADDR1=22
  • AUXADDR2=22
  • AUXADDR3=22
  • AUXADDR4=22
  • AUXSDO=22
  • AUXSDOIN=21
  • BKST=22
  • CLK=22
  • CS=22
  • DOUT=22
  • DQSOUTP=20
  • IDATAIN=20
  • IOCLK0=22
  • MEMUPDATE=22
  • ODATAIN=22
  • SDI=22
  • T=22
  • TOUT=22
IODRP2_MCB_IODRP2_MCB
  • ADD=22
  • AUXADDR0=22
  • AUXADDR1=22
  • AUXADDR2=22
  • AUXADDR3=22
  • AUXADDR4=22
  • AUXSDO=22
  • AUXSDOIN=21
  • BKST=22
  • CLK=22
  • CS=22
  • DOUT=22
  • DQSOUTP=20
  • IDATAIN=20
  • IOCLK0=22
  • MEMUPDATE=22
  • ODATAIN=22
  • SDI=22
  • T=22
  • TOUT=22
LUT5
  • A1=622
  • A2=1496
  • A3=1617
  • A4=762
  • A5=1843
  • O5=3023
LUT6
  • A1=3114
  • A2=4602
  • A3=6475
  • A4=7130
  • A5=7275
  • A6=7491
  • O6=7515
LUT_OR_MEM5
  • A1=168
  • A2=168
  • A3=168
  • A4=167
  • A5=181
  • CLK=163
  • DI1=163
  • O5=171
  • WA1=32
  • WA2=32
  • WA3=32
  • WA4=32
  • WA5=32
  • WE=163
LUT_OR_MEM6
  • A1=193
  • A2=194
  • A3=196
  • A4=201
  • A5=205
  • A6=205
  • CLK=169
  • DI2=169
  • O6=189
  • WA1=32
  • WA2=32
  • WA3=32
  • WA4=32
  • WA5=32
  • WA6=32
  • WE=169
MCB
  • ADDR0=1
  • ADDR1=1
  • ADDR10=1
  • ADDR11=1
  • ADDR12=1
  • ADDR2=1
  • ADDR3=1
  • ADDR4=1
  • ADDR5=1
  • ADDR6=1
  • ADDR7=1
  • ADDR8=1
  • ADDR9=1
  • BA0=1
  • BA1=1
  • BA2=1
  • CAS=1
  • CKE=1
  • DQI0=1
  • DQI1=1
  • DQI10=1
  • DQI11=1
  • DQI12=1
  • DQI13=1
  • DQI14=1
  • DQI15=1
  • DQI2=1
  • DQI3=1
  • DQI4=1
  • DQI5=1
  • DQI6=1
  • DQI7=1
  • DQI8=1
  • DQI9=1
  • DQIOWEN0=1
  • DQON0=1
  • DQON1=1
  • DQON10=1
  • DQON11=1
  • DQON12=1
  • DQON13=1
  • DQON14=1
  • DQON15=1
  • DQON2=1
  • DQON3=1
  • DQON4=1
  • DQON5=1
  • DQON6=1
  • DQON7=1
  • DQON8=1
  • DQON9=1
  • DQOP0=1
  • DQOP1=1
  • DQOP10=1
  • DQOP11=1
  • DQOP12=1
  • DQOP13=1
  • DQOP14=1
  • DQOP15=1
  • DQOP2=1
  • DQOP3=1
  • DQOP4=1
  • DQOP5=1
  • DQOP6=1
  • DQOP7=1
  • DQOP8=1
  • DQOP9=1
  • DQSIOIN=1
  • DQSIOIP=1
  • DQSIOWEN90N=1
  • DQSIOWEN90P=1
  • IOIDRPADD=1
  • IOIDRPADDR0=1
  • IOIDRPADDR1=1
  • IOIDRPADDR2=1
  • IOIDRPADDR3=1
  • IOIDRPADDR4=1
  • IOIDRPBROADCAST=1
  • IOIDRPCLK=1
  • IOIDRPCS=1
  • IOIDRPSDI=1
  • IOIDRPSDO=1
  • IOIDRPTRAIN=1
  • IOIDRPUPDATE=1
  • LDMN=1
  • LDMP=1
  • ODT=1
  • P0ARBEN=1
  • P0CMDBA0=1
  • P0CMDBA1=1
  • P0CMDBA2=1
  • P0CMDBL0=1
  • P0CMDBL1=1
  • P0CMDBL2=1
  • P0CMDBL3=1
  • P0CMDBL4=1
  • P0CMDBL5=1
  • P0CMDCA0=1
  • P0CMDCA1=1
  • P0CMDCA10=1
  • P0CMDCA11=1
  • P0CMDCA2=1
  • P0CMDCA3=1
  • P0CMDCA4=1
  • P0CMDCA5=1
  • P0CMDCA6=1
  • P0CMDCA7=1
  • P0CMDCA8=1
  • P0CMDCA9=1
  • P0CMDCLK=1
  • P0CMDEN=1
  • P0CMDFULL=1
  • P0CMDINSTR0=1
  • P0CMDINSTR1=1
  • P0CMDINSTR2=1
  • P0CMDRA0=1
  • P0CMDRA1=1
  • P0CMDRA10=1
  • P0CMDRA11=1
  • P0CMDRA12=1
  • P0CMDRA13=1
  • P0CMDRA14=1
  • P0CMDRA2=1
  • P0CMDRA3=1
  • P0CMDRA4=1
  • P0CMDRA5=1
  • P0CMDRA6=1
  • P0CMDRA7=1
  • P0CMDRA8=1
  • P0CMDRA9=1
  • P0RDCLK=1
  • P0RDEN=1
  • P0RWRMASK0=1
  • P0RWRMASK1=1
  • P0RWRMASK2=1
  • P0RWRMASK3=1
  • P0WRCLK=1
  • P0WRDATA0=1
  • P0WRDATA1=1
  • P0WRDATA10=1
  • P0WRDATA11=1
  • P0WRDATA12=1
  • P0WRDATA13=1
  • P0WRDATA14=1
  • P0WRDATA15=1
  • P0WRDATA16=1
  • P0WRDATA17=1
  • P0WRDATA18=1
  • P0WRDATA19=1
  • P0WRDATA2=1
  • P0WRDATA20=1
  • P0WRDATA21=1
  • P0WRDATA22=1
  • P0WRDATA23=1
  • P0WRDATA24=1
  • P0WRDATA25=1
  • P0WRDATA26=1
  • P0WRDATA27=1
  • P0WRDATA28=1
  • P0WRDATA29=1
  • P0WRDATA3=1
  • P0WRDATA30=1
  • P0WRDATA31=1
  • P0WRDATA4=1
  • P0WRDATA5=1
  • P0WRDATA6=1
  • P0WRDATA7=1
  • P0WRDATA8=1
  • P0WRDATA9=1
  • P0WREMPTY=1
  • P0WREN=1
  • P1ARBEN=1
  • P1CMDBA0=1
  • P1CMDBA1=1
  • P1CMDBA2=1
  • P1CMDBL0=1
  • P1CMDBL1=1
  • P1CMDBL2=1
  • P1CMDBL3=1
  • P1CMDBL4=1
  • P1CMDBL5=1
  • P1CMDCA0=1
  • P1CMDCA1=1
  • P1CMDCA10=1
  • P1CMDCA11=1
  • P1CMDCA2=1
  • P1CMDCA3=1
  • P1CMDCA4=1
  • P1CMDCA5=1
  • P1CMDCA6=1
  • P1CMDCA7=1
  • P1CMDCA8=1
  • P1CMDCA9=1
  • P1CMDCLK=1
  • P1CMDEN=1
  • P1CMDFULL=1
  • P1CMDINSTR0=1
  • P1CMDINSTR1=1
  • P1CMDINSTR2=1
  • P1CMDRA0=1
  • P1CMDRA1=1
  • P1CMDRA10=1
  • P1CMDRA11=1
  • P1CMDRA12=1
  • P1CMDRA13=1
  • P1CMDRA14=1
  • P1CMDRA2=1
  • P1CMDRA3=1
  • P1CMDRA4=1
  • P1CMDRA5=1
  • P1CMDRA6=1
  • P1CMDRA7=1
  • P1CMDRA8=1
  • P1CMDRA9=1
  • P1RDCLK=1
  • P1RDDATA0=1
  • P1RDDATA1=1
  • P1RDDATA10=1
  • P1RDDATA11=1
  • P1RDDATA12=1
  • P1RDDATA13=1
  • P1RDDATA14=1
  • P1RDDATA15=1
  • P1RDDATA16=1
  • P1RDDATA17=1
  • P1RDDATA18=1
  • P1RDDATA19=1
  • P1RDDATA2=1
  • P1RDDATA20=1
  • P1RDDATA21=1
  • P1RDDATA22=1
  • P1RDDATA23=1
  • P1RDDATA24=1
  • P1RDDATA25=1
  • P1RDDATA26=1
  • P1RDDATA27=1
  • P1RDDATA28=1
  • P1RDDATA29=1
  • P1RDDATA3=1
  • P1RDDATA30=1
  • P1RDDATA31=1
  • P1RDDATA4=1
  • P1RDDATA5=1
  • P1RDDATA6=1
  • P1RDDATA7=1
  • P1RDDATA8=1
  • P1RDDATA9=1
  • P1RDEMPTY=1
  • P1RDEN=1
  • P1RWRMASK0=1
  • P1RWRMASK1=1
  • P1RWRMASK2=1
  • P1RWRMASK3=1
  • P1WRCLK=1
  • P1WRDATA0=1
  • P1WRDATA1=1
  • P1WRDATA10=1
  • P1WRDATA11=1
  • P1WRDATA12=1
  • P1WRDATA13=1
  • P1WRDATA14=1
  • P1WRDATA15=1
  • P1WRDATA16=1
  • P1WRDATA17=1
  • P1WRDATA18=1
  • P1WRDATA19=1
  • P1WRDATA2=1
  • P1WRDATA20=1
  • P1WRDATA21=1
  • P1WRDATA22=1
  • P1WRDATA23=1
  • P1WRDATA24=1
  • P1WRDATA25=1
  • P1WRDATA26=1
  • P1WRDATA27=1
  • P1WRDATA28=1
  • P1WRDATA29=1
  • P1WRDATA3=1
  • P1WRDATA30=1
  • P1WRDATA31=1
  • P1WRDATA4=1
  • P1WRDATA5=1
  • P1WRDATA6=1
  • P1WRDATA7=1
  • P1WRDATA8=1
  • P1WRDATA9=1
  • P1WREN=1
  • P2ARBEN=1
  • P2CLK=1
  • P2CMDBA0=1
  • P2CMDBA1=1
  • P2CMDBA2=1
  • P2CMDBL0=1
  • P2CMDBL1=1
  • P2CMDBL2=1
  • P2CMDBL3=1
  • P2CMDBL4=1
  • P2CMDBL5=1
  • P2CMDCA0=1
  • P2CMDCA1=1
  • P2CMDCA10=1
  • P2CMDCA11=1
  • P2CMDCA2=1
  • P2CMDCA3=1
  • P2CMDCA4=1
  • P2CMDCA5=1
  • P2CMDCA6=1
  • P2CMDCA7=1
  • P2CMDCA8=1
  • P2CMDCA9=1
  • P2CMDCLK=1
  • P2CMDEN=1
  • P2CMDINSTR0=1
  • P2CMDINSTR1=1
  • P2CMDINSTR2=1
  • P2CMDRA0=1
  • P2CMDRA1=1
  • P2CMDRA10=1
  • P2CMDRA11=1
  • P2CMDRA12=1
  • P2CMDRA13=1
  • P2CMDRA14=1
  • P2CMDRA2=1
  • P2CMDRA3=1
  • P2CMDRA4=1
  • P2CMDRA5=1
  • P2CMDRA6=1
  • P2CMDRA7=1
  • P2CMDRA8=1
  • P2CMDRA9=1
  • P2EN=1
  • P2WRDATA0=1
  • P2WRDATA1=1
  • P2WRDATA10=1
  • P2WRDATA11=1
  • P2WRDATA12=1
  • P2WRDATA13=1
  • P2WRDATA14=1
  • P2WRDATA15=1
  • P2WRDATA16=1
  • P2WRDATA17=1
  • P2WRDATA18=1
  • P2WRDATA19=1
  • P2WRDATA2=1
  • P2WRDATA20=1
  • P2WRDATA21=1
  • P2WRDATA22=1
  • P2WRDATA23=1
  • P2WRDATA24=1
  • P2WRDATA25=1
  • P2WRDATA26=1
  • P2WRDATA27=1
  • P2WRDATA28=1
  • P2WRDATA29=1
  • P2WRDATA3=1
  • P2WRDATA30=1
  • P2WRDATA31=1
  • P2WRDATA4=1
  • P2WRDATA5=1
  • P2WRDATA6=1
  • P2WRDATA7=1
  • P2WRDATA8=1
  • P2WRDATA9=1
  • P2WRMASK0=1
  • P2WRMASK1=1
  • P2WRMASK2=1
  • P2WRMASK3=1
  • P3ARBEN=1
  • P3CLK=1
  • P3CMDBA0=1
  • P3CMDBA1=1
  • P3CMDBA2=1
  • P3CMDBL0=1
  • P3CMDBL1=1
  • P3CMDBL2=1
  • P3CMDBL3=1
  • P3CMDBL4=1
  • P3CMDBL5=1
  • P3CMDCA0=1
  • P3CMDCA1=1
  • P3CMDCA10=1
  • P3CMDCA11=1
  • P3CMDCA2=1
  • P3CMDCA3=1
  • P3CMDCA4=1
  • P3CMDCA5=1
  • P3CMDCA6=1
  • P3CMDCA7=1
  • P3CMDCA8=1
  • P3CMDCA9=1
  • P3CMDCLK=1
  • P3CMDEN=1
  • P3CMDINSTR0=1
  • P3CMDINSTR1=1
  • P3CMDINSTR2=1
  • P3CMDRA0=1
  • P3CMDRA1=1
  • P3CMDRA10=1
  • P3CMDRA11=1
  • P3CMDRA12=1
  • P3CMDRA13=1
  • P3CMDRA14=1
  • P3CMDRA2=1
  • P3CMDRA3=1
  • P3CMDRA4=1
  • P3CMDRA5=1
  • P3CMDRA6=1
  • P3CMDRA7=1
  • P3CMDRA8=1
  • P3CMDRA9=1
  • P3EN=1
  • P3WRDATA0=1
  • P3WRDATA1=1
  • P3WRDATA10=1
  • P3WRDATA11=1
  • P3WRDATA12=1
  • P3WRDATA13=1
  • P3WRDATA14=1
  • P3WRDATA15=1
  • P3WRDATA16=1
  • P3WRDATA17=1
  • P3WRDATA18=1
  • P3WRDATA19=1
  • P3WRDATA2=1
  • P3WRDATA20=1
  • P3WRDATA21=1
  • P3WRDATA22=1
  • P3WRDATA23=1
  • P3WRDATA24=1
  • P3WRDATA25=1
  • P3WRDATA26=1
  • P3WRDATA27=1
  • P3WRDATA28=1
  • P3WRDATA29=1
  • P3WRDATA3=1
  • P3WRDATA30=1
  • P3WRDATA31=1
  • P3WRDATA4=1
  • P3WRDATA5=1
  • P3WRDATA6=1
  • P3WRDATA7=1
  • P3WRDATA8=1
  • P3WRDATA9=1
  • P3WRMASK0=1
  • P3WRMASK1=1
  • P3WRMASK2=1
  • P3WRMASK3=1
  • P4ARBEN=1
  • P4CLK=1
  • P4CMDBA0=1
  • P4CMDBA1=1
  • P4CMDBA2=1
  • P4CMDBL0=1
  • P4CMDBL1=1
  • P4CMDBL2=1
  • P4CMDBL3=1
  • P4CMDBL4=1
  • P4CMDBL5=1
  • P4CMDCA0=1
  • P4CMDCA1=1
  • P4CMDCA10=1
  • P4CMDCA11=1
  • P4CMDCA2=1
  • P4CMDCA3=1
  • P4CMDCA4=1
  • P4CMDCA5=1
  • P4CMDCA6=1
  • P4CMDCA7=1
  • P4CMDCA8=1
  • P4CMDCA9=1
  • P4CMDCLK=1
  • P4CMDEN=1
  • P4CMDINSTR0=1
  • P4CMDINSTR1=1
  • P4CMDINSTR2=1
  • P4CMDRA0=1
  • P4CMDRA1=1
  • P4CMDRA10=1
  • P4CMDRA11=1
  • P4CMDRA12=1
  • P4CMDRA13=1
  • P4CMDRA14=1
  • P4CMDRA2=1
  • P4CMDRA3=1
  • P4CMDRA4=1
  • P4CMDRA5=1
  • P4CMDRA6=1
  • P4CMDRA7=1
  • P4CMDRA8=1
  • P4CMDRA9=1
  • P4EN=1
  • P4WRDATA0=1
  • P4WRDATA1=1
  • P4WRDATA10=1
  • P4WRDATA11=1
  • P4WRDATA12=1
  • P4WRDATA13=1
  • P4WRDATA14=1
  • P4WRDATA15=1
  • P4WRDATA16=1
  • P4WRDATA17=1
  • P4WRDATA18=1
  • P4WRDATA19=1
  • P4WRDATA2=1
  • P4WRDATA20=1
  • P4WRDATA21=1
  • P4WRDATA22=1
  • P4WRDATA23=1
  • P4WRDATA24=1
  • P4WRDATA25=1
  • P4WRDATA26=1
  • P4WRDATA27=1
  • P4WRDATA28=1
  • P4WRDATA29=1
  • P4WRDATA3=1
  • P4WRDATA30=1
  • P4WRDATA31=1
  • P4WRDATA4=1
  • P4WRDATA5=1
  • P4WRDATA6=1
  • P4WRDATA7=1
  • P4WRDATA8=1
  • P4WRDATA9=1
  • P4WRMASK0=1
  • P4WRMASK1=1
  • P4WRMASK2=1
  • P4WRMASK3=1
  • P5ARBEN=1
  • P5CLK=1
  • P5CMDBA0=1
  • P5CMDBA1=1
  • P5CMDBA2=1
  • P5CMDBL0=1
  • P5CMDBL1=1
  • P5CMDBL2=1
  • P5CMDBL3=1
  • P5CMDBL4=1
  • P5CMDBL5=1
  • P5CMDCA0=1
  • P5CMDCA1=1
  • P5CMDCA10=1
  • P5CMDCA11=1
  • P5CMDCA2=1
  • P5CMDCA3=1
  • P5CMDCA4=1
  • P5CMDCA5=1
  • P5CMDCA6=1
  • P5CMDCA7=1
  • P5CMDCA8=1
  • P5CMDCA9=1
  • P5CMDCLK=1
  • P5CMDEN=1
  • P5CMDINSTR0=1
  • P5CMDINSTR1=1
  • P5CMDINSTR2=1
  • P5CMDRA0=1
  • P5CMDRA1=1
  • P5CMDRA10=1
  • P5CMDRA11=1
  • P5CMDRA12=1
  • P5CMDRA13=1
  • P5CMDRA14=1
  • P5CMDRA2=1
  • P5CMDRA3=1
  • P5CMDRA4=1
  • P5CMDRA5=1
  • P5CMDRA6=1
  • P5CMDRA7=1
  • P5CMDRA8=1
  • P5CMDRA9=1
  • P5EN=1
  • P5WRDATA0=1
  • P5WRDATA1=1
  • P5WRDATA10=1
  • P5WRDATA11=1
  • P5WRDATA12=1
  • P5WRDATA13=1
  • P5WRDATA14=1
  • P5WRDATA15=1
  • P5WRDATA16=1
  • P5WRDATA17=1
  • P5WRDATA18=1
  • P5WRDATA19=1
  • P5WRDATA2=1
  • P5WRDATA20=1
  • P5WRDATA21=1
  • P5WRDATA22=1
  • P5WRDATA23=1
  • P5WRDATA24=1
  • P5WRDATA25=1
  • P5WRDATA26=1
  • P5WRDATA27=1
  • P5WRDATA28=1
  • P5WRDATA29=1
  • P5WRDATA3=1
  • P5WRDATA30=1
  • P5WRDATA31=1
  • P5WRDATA4=1
  • P5WRDATA5=1
  • P5WRDATA6=1
  • P5WRDATA7=1
  • P5WRDATA8=1
  • P5WRDATA9=1
  • P5WRMASK0=1
  • P5WRMASK1=1
  • P5WRMASK2=1
  • P5WRMASK3=1
  • PLLCE0=1
  • PLLCE1=1
  • PLLCLK0=1
  • PLLCLK1=1
  • PLLLOCK=1
  • RAS=1
  • RECAL=1
  • SELFREFRESHENTER=1
  • SELFREFRESHMODE=1
  • SYSRST=1
  • UDMN=1
  • UDMP=1
  • UDQSIOIN=1
  • UDQSIOIP=1
  • UIADD=1
  • UIADDR0=1
  • UIADDR1=1
  • UIADDR2=1
  • UIADDR3=1
  • UIADDR4=1
  • UIBROADCAST=1
  • UICLK=1
  • UICMD=1
  • UICMDEN=1
  • UICMDIN=1
  • UICS=1
  • UIDONECAL=1
  • UIDQCOUNT0=1
  • UIDQCOUNT1=1
  • UIDQCOUNT2=1
  • UIDQCOUNT3=1
  • UIDQLOWERDEC=1
  • UIDQLOWERINC=1
  • UIDQUPPERDEC=1
  • UIDQUPPERINC=1
  • UIDRPUPDATE=1
  • UILDQSDEC=1
  • UILDQSINC=1
  • UIREAD=1
  • UISDI=1
  • UIUDQSDEC=1
  • UIUDQSINC=1
  • UODONECAL=1
  • UOREFRSHFLAG=1
  • UOSDO=1
  • WE=1
MCB_MCB
  • ADDR0=1
  • ADDR1=1
  • ADDR10=1
  • ADDR11=1
  • ADDR12=1
  • ADDR2=1
  • ADDR3=1
  • ADDR4=1
  • ADDR5=1
  • ADDR6=1
  • ADDR7=1
  • ADDR8=1
  • ADDR9=1
  • BA0=1
  • BA1=1
  • BA2=1
  • CAS=1
  • CKE=1
  • DQI0=1
  • DQI1=1
  • DQI10=1
  • DQI11=1
  • DQI12=1
  • DQI13=1
  • DQI14=1
  • DQI15=1
  • DQI2=1
  • DQI3=1
  • DQI4=1
  • DQI5=1
  • DQI6=1
  • DQI7=1
  • DQI8=1
  • DQI9=1
  • DQIOWEN0=1
  • DQON0=1
  • DQON1=1
  • DQON10=1
  • DQON11=1
  • DQON12=1
  • DQON13=1
  • DQON14=1
  • DQON15=1
  • DQON2=1
  • DQON3=1
  • DQON4=1
  • DQON5=1
  • DQON6=1
  • DQON7=1
  • DQON8=1
  • DQON9=1
  • DQOP0=1
  • DQOP1=1
  • DQOP10=1
  • DQOP11=1
  • DQOP12=1
  • DQOP13=1
  • DQOP14=1
  • DQOP15=1
  • DQOP2=1
  • DQOP3=1
  • DQOP4=1
  • DQOP5=1
  • DQOP6=1
  • DQOP7=1
  • DQOP8=1
  • DQOP9=1
  • DQSIOIN=1
  • DQSIOIP=1
  • DQSIOWEN90N=1
  • DQSIOWEN90P=1
  • IOIDRPADD=1
  • IOIDRPADDR0=1
  • IOIDRPADDR1=1
  • IOIDRPADDR2=1
  • IOIDRPADDR3=1
  • IOIDRPADDR4=1
  • IOIDRPBROADCAST=1
  • IOIDRPCLK=1
  • IOIDRPCS=1
  • IOIDRPSDI=1
  • IOIDRPSDO=1
  • IOIDRPTRAIN=1
  • IOIDRPUPDATE=1
  • LDMN=1
  • LDMP=1
  • ODT=1
  • P0ARBEN=1
  • P0CMDBA0=1
  • P0CMDBA1=1
  • P0CMDBA2=1
  • P0CMDBL0=1
  • P0CMDBL1=1
  • P0CMDBL2=1
  • P0CMDBL3=1
  • P0CMDBL4=1
  • P0CMDBL5=1
  • P0CMDCA0=1
  • P0CMDCA1=1
  • P0CMDCA10=1
  • P0CMDCA11=1
  • P0CMDCA2=1
  • P0CMDCA3=1
  • P0CMDCA4=1
  • P0CMDCA5=1
  • P0CMDCA6=1
  • P0CMDCA7=1
  • P0CMDCA8=1
  • P0CMDCA9=1
  • P0CMDCLK=1
  • P0CMDEN=1
  • P0CMDFULL=1
  • P0CMDINSTR0=1
  • P0CMDINSTR1=1
  • P0CMDINSTR2=1
  • P0CMDRA0=1
  • P0CMDRA1=1
  • P0CMDRA10=1
  • P0CMDRA11=1
  • P0CMDRA12=1
  • P0CMDRA13=1
  • P0CMDRA14=1
  • P0CMDRA2=1
  • P0CMDRA3=1
  • P0CMDRA4=1
  • P0CMDRA5=1
  • P0CMDRA6=1
  • P0CMDRA7=1
  • P0CMDRA8=1
  • P0CMDRA9=1
  • P0RDCLK=1
  • P0RDEN=1
  • P0RWRMASK0=1
  • P0RWRMASK1=1
  • P0RWRMASK2=1
  • P0RWRMASK3=1
  • P0WRCLK=1
  • P0WRDATA0=1
  • P0WRDATA1=1
  • P0WRDATA10=1
  • P0WRDATA11=1
  • P0WRDATA12=1
  • P0WRDATA13=1
  • P0WRDATA14=1
  • P0WRDATA15=1
  • P0WRDATA16=1
  • P0WRDATA17=1
  • P0WRDATA18=1
  • P0WRDATA19=1
  • P0WRDATA2=1
  • P0WRDATA20=1
  • P0WRDATA21=1
  • P0WRDATA22=1
  • P0WRDATA23=1
  • P0WRDATA24=1
  • P0WRDATA25=1
  • P0WRDATA26=1
  • P0WRDATA27=1
  • P0WRDATA28=1
  • P0WRDATA29=1
  • P0WRDATA3=1
  • P0WRDATA30=1
  • P0WRDATA31=1
  • P0WRDATA4=1
  • P0WRDATA5=1
  • P0WRDATA6=1
  • P0WRDATA7=1
  • P0WRDATA8=1
  • P0WRDATA9=1
  • P0WREMPTY=1
  • P0WREN=1
  • P1ARBEN=1
  • P1CMDBA0=1
  • P1CMDBA1=1
  • P1CMDBA2=1
  • P1CMDBL0=1
  • P1CMDBL1=1
  • P1CMDBL2=1
  • P1CMDBL3=1
  • P1CMDBL4=1
  • P1CMDBL5=1
  • P1CMDCA0=1
  • P1CMDCA1=1
  • P1CMDCA10=1
  • P1CMDCA11=1
  • P1CMDCA2=1
  • P1CMDCA3=1
  • P1CMDCA4=1
  • P1CMDCA5=1
  • P1CMDCA6=1
  • P1CMDCA7=1
  • P1CMDCA8=1
  • P1CMDCA9=1
  • P1CMDCLK=1
  • P1CMDEN=1
  • P1CMDFULL=1
  • P1CMDINSTR0=1
  • P1CMDINSTR1=1
  • P1CMDINSTR2=1
  • P1CMDRA0=1
  • P1CMDRA1=1
  • P1CMDRA10=1
  • P1CMDRA11=1
  • P1CMDRA12=1
  • P1CMDRA13=1
  • P1CMDRA14=1
  • P1CMDRA2=1
  • P1CMDRA3=1
  • P1CMDRA4=1
  • P1CMDRA5=1
  • P1CMDRA6=1
  • P1CMDRA7=1
  • P1CMDRA8=1
  • P1CMDRA9=1
  • P1RDCLK=1
  • P1RDDATA0=1
  • P1RDDATA1=1
  • P1RDDATA10=1
  • P1RDDATA11=1
  • P1RDDATA12=1
  • P1RDDATA13=1
  • P1RDDATA14=1
  • P1RDDATA15=1
  • P1RDDATA16=1
  • P1RDDATA17=1
  • P1RDDATA18=1
  • P1RDDATA19=1
  • P1RDDATA2=1
  • P1RDDATA20=1
  • P1RDDATA21=1
  • P1RDDATA22=1
  • P1RDDATA23=1
  • P1RDDATA24=1
  • P1RDDATA25=1
  • P1RDDATA26=1
  • P1RDDATA27=1
  • P1RDDATA28=1
  • P1RDDATA29=1
  • P1RDDATA3=1
  • P1RDDATA30=1
  • P1RDDATA31=1
  • P1RDDATA4=1
  • P1RDDATA5=1
  • P1RDDATA6=1
  • P1RDDATA7=1
  • P1RDDATA8=1
  • P1RDDATA9=1
  • P1RDEMPTY=1
  • P1RDEN=1
  • P1RWRMASK0=1
  • P1RWRMASK1=1
  • P1RWRMASK2=1
  • P1RWRMASK3=1
  • P1WRCLK=1
  • P1WRDATA0=1
  • P1WRDATA1=1
  • P1WRDATA10=1
  • P1WRDATA11=1
  • P1WRDATA12=1
  • P1WRDATA13=1
  • P1WRDATA14=1
  • P1WRDATA15=1
  • P1WRDATA16=1
  • P1WRDATA17=1
  • P1WRDATA18=1
  • P1WRDATA19=1
  • P1WRDATA2=1
  • P1WRDATA20=1
  • P1WRDATA21=1
  • P1WRDATA22=1
  • P1WRDATA23=1
  • P1WRDATA24=1
  • P1WRDATA25=1
  • P1WRDATA26=1
  • P1WRDATA27=1
  • P1WRDATA28=1
  • P1WRDATA29=1
  • P1WRDATA3=1
  • P1WRDATA30=1
  • P1WRDATA31=1
  • P1WRDATA4=1
  • P1WRDATA5=1
  • P1WRDATA6=1
  • P1WRDATA7=1
  • P1WRDATA8=1
  • P1WRDATA9=1
  • P1WREN=1
  • P2ARBEN=1
  • P2CLK=1
  • P2CMDBA0=1
  • P2CMDBA1=1
  • P2CMDBA2=1
  • P2CMDBL0=1
  • P2CMDBL1=1
  • P2CMDBL2=1
  • P2CMDBL3=1
  • P2CMDBL4=1
  • P2CMDBL5=1
  • P2CMDCA0=1
  • P2CMDCA1=1
  • P2CMDCA10=1
  • P2CMDCA11=1
  • P2CMDCA2=1
  • P2CMDCA3=1
  • P2CMDCA4=1
  • P2CMDCA5=1
  • P2CMDCA6=1
  • P2CMDCA7=1
  • P2CMDCA8=1
  • P2CMDCA9=1
  • P2CMDCLK=1
  • P2CMDEN=1
  • P2CMDINSTR0=1
  • P2CMDINSTR1=1
  • P2CMDINSTR2=1
  • P2CMDRA0=1
  • P2CMDRA1=1
  • P2CMDRA10=1
  • P2CMDRA11=1
  • P2CMDRA12=1
  • P2CMDRA13=1
  • P2CMDRA14=1
  • P2CMDRA2=1
  • P2CMDRA3=1
  • P2CMDRA4=1
  • P2CMDRA5=1
  • P2CMDRA6=1
  • P2CMDRA7=1
  • P2CMDRA8=1
  • P2CMDRA9=1
  • P2EN=1
  • P2WRDATA0=1
  • P2WRDATA1=1
  • P2WRDATA10=1
  • P2WRDATA11=1
  • P2WRDATA12=1
  • P2WRDATA13=1
  • P2WRDATA14=1
  • P2WRDATA15=1
  • P2WRDATA16=1
  • P2WRDATA17=1
  • P2WRDATA18=1
  • P2WRDATA19=1
  • P2WRDATA2=1
  • P2WRDATA20=1
  • P2WRDATA21=1
  • P2WRDATA22=1
  • P2WRDATA23=1
  • P2WRDATA24=1
  • P2WRDATA25=1
  • P2WRDATA26=1
  • P2WRDATA27=1
  • P2WRDATA28=1
  • P2WRDATA29=1
  • P2WRDATA3=1
  • P2WRDATA30=1
  • P2WRDATA31=1
  • P2WRDATA4=1
  • P2WRDATA5=1
  • P2WRDATA6=1
  • P2WRDATA7=1
  • P2WRDATA8=1
  • P2WRDATA9=1
  • P2WRMASK0=1
  • P2WRMASK1=1
  • P2WRMASK2=1
  • P2WRMASK3=1
  • P3ARBEN=1
  • P3CLK=1
  • P3CMDBA0=1
  • P3CMDBA1=1
  • P3CMDBA2=1
  • P3CMDBL0=1
  • P3CMDBL1=1
  • P3CMDBL2=1
  • P3CMDBL3=1
  • P3CMDBL4=1
  • P3CMDBL5=1
  • P3CMDCA0=1
  • P3CMDCA1=1
  • P3CMDCA10=1
  • P3CMDCA11=1
  • P3CMDCA2=1
  • P3CMDCA3=1
  • P3CMDCA4=1
  • P3CMDCA5=1
  • P3CMDCA6=1
  • P3CMDCA7=1
  • P3CMDCA8=1
  • P3CMDCA9=1
  • P3CMDCLK=1
  • P3CMDEN=1
  • P3CMDINSTR0=1
  • P3CMDINSTR1=1
  • P3CMDINSTR2=1
  • P3CMDRA0=1
  • P3CMDRA1=1
  • P3CMDRA10=1
  • P3CMDRA11=1
  • P3CMDRA12=1
  • P3CMDRA13=1
  • P3CMDRA14=1
  • P3CMDRA2=1
  • P3CMDRA3=1
  • P3CMDRA4=1
  • P3CMDRA5=1
  • P3CMDRA6=1
  • P3CMDRA7=1
  • P3CMDRA8=1
  • P3CMDRA9=1
  • P3EN=1
  • P3WRDATA0=1
  • P3WRDATA1=1
  • P3WRDATA10=1
  • P3WRDATA11=1
  • P3WRDATA12=1
  • P3WRDATA13=1
  • P3WRDATA14=1
  • P3WRDATA15=1
  • P3WRDATA16=1
  • P3WRDATA17=1
  • P3WRDATA18=1
  • P3WRDATA19=1
  • P3WRDATA2=1
  • P3WRDATA20=1
  • P3WRDATA21=1
  • P3WRDATA22=1
  • P3WRDATA23=1
  • P3WRDATA24=1
  • P3WRDATA25=1
  • P3WRDATA26=1
  • P3WRDATA27=1
  • P3WRDATA28=1
  • P3WRDATA29=1
  • P3WRDATA3=1
  • P3WRDATA30=1
  • P3WRDATA31=1
  • P3WRDATA4=1
  • P3WRDATA5=1
  • P3WRDATA6=1
  • P3WRDATA7=1
  • P3WRDATA8=1
  • P3WRDATA9=1
  • P3WRMASK0=1
  • P3WRMASK1=1
  • P3WRMASK2=1
  • P3WRMASK3=1
  • P4ARBEN=1
  • P4CLK=1
  • P4CMDBA0=1
  • P4CMDBA1=1
  • P4CMDBA2=1
  • P4CMDBL0=1
  • P4CMDBL1=1
  • P4CMDBL2=1
  • P4CMDBL3=1
  • P4CMDBL4=1
  • P4CMDBL5=1
  • P4CMDCA0=1
  • P4CMDCA1=1
  • P4CMDCA10=1
  • P4CMDCA11=1
  • P4CMDCA2=1
  • P4CMDCA3=1
  • P4CMDCA4=1
  • P4CMDCA5=1
  • P4CMDCA6=1
  • P4CMDCA7=1
  • P4CMDCA8=1
  • P4CMDCA9=1
  • P4CMDCLK=1
  • P4CMDEN=1
  • P4CMDINSTR0=1
  • P4CMDINSTR1=1
  • P4CMDINSTR2=1
  • P4CMDRA0=1
  • P4CMDRA1=1
  • P4CMDRA10=1
  • P4CMDRA11=1
  • P4CMDRA12=1
  • P4CMDRA13=1
  • P4CMDRA14=1
  • P4CMDRA2=1
  • P4CMDRA3=1
  • P4CMDRA4=1
  • P4CMDRA5=1
  • P4CMDRA6=1
  • P4CMDRA7=1
  • P4CMDRA8=1
  • P4CMDRA9=1
  • P4EN=1
  • P4WRDATA0=1
  • P4WRDATA1=1
  • P4WRDATA10=1
  • P4WRDATA11=1
  • P4WRDATA12=1
  • P4WRDATA13=1
  • P4WRDATA14=1
  • P4WRDATA15=1
  • P4WRDATA16=1
  • P4WRDATA17=1
  • P4WRDATA18=1
  • P4WRDATA19=1
  • P4WRDATA2=1
  • P4WRDATA20=1
  • P4WRDATA21=1
  • P4WRDATA22=1
  • P4WRDATA23=1
  • P4WRDATA24=1
  • P4WRDATA25=1
  • P4WRDATA26=1
  • P4WRDATA27=1
  • P4WRDATA28=1
  • P4WRDATA29=1
  • P4WRDATA3=1
  • P4WRDATA30=1
  • P4WRDATA31=1
  • P4WRDATA4=1
  • P4WRDATA5=1
  • P4WRDATA6=1
  • P4WRDATA7=1
  • P4WRDATA8=1
  • P4WRDATA9=1
  • P4WRMASK0=1
  • P4WRMASK1=1
  • P4WRMASK2=1
  • P4WRMASK3=1
  • P5ARBEN=1
  • P5CLK=1
  • P5CMDBA0=1
  • P5CMDBA1=1
  • P5CMDBA2=1
  • P5CMDBL0=1
  • P5CMDBL1=1
  • P5CMDBL2=1
  • P5CMDBL3=1
  • P5CMDBL4=1
  • P5CMDBL5=1
  • P5CMDCA0=1
  • P5CMDCA1=1
  • P5CMDCA10=1
  • P5CMDCA11=1
  • P5CMDCA2=1
  • P5CMDCA3=1
  • P5CMDCA4=1
  • P5CMDCA5=1
  • P5CMDCA6=1
  • P5CMDCA7=1
  • P5CMDCA8=1
  • P5CMDCA9=1
  • P5CMDCLK=1
  • P5CMDEN=1
  • P5CMDINSTR0=1
  • P5CMDINSTR1=1
  • P5CMDINSTR2=1
  • P5CMDRA0=1
  • P5CMDRA1=1
  • P5CMDRA10=1
  • P5CMDRA11=1
  • P5CMDRA12=1
  • P5CMDRA13=1
  • P5CMDRA14=1
  • P5CMDRA2=1
  • P5CMDRA3=1
  • P5CMDRA4=1
  • P5CMDRA5=1
  • P5CMDRA6=1
  • P5CMDRA7=1
  • P5CMDRA8=1
  • P5CMDRA9=1
  • P5EN=1
  • P5WRDATA0=1
  • P5WRDATA1=1
  • P5WRDATA10=1
  • P5WRDATA11=1
  • P5WRDATA12=1
  • P5WRDATA13=1
  • P5WRDATA14=1
  • P5WRDATA15=1
  • P5WRDATA16=1
  • P5WRDATA17=1
  • P5WRDATA18=1
  • P5WRDATA19=1
  • P5WRDATA2=1
  • P5WRDATA20=1
  • P5WRDATA21=1
  • P5WRDATA22=1
  • P5WRDATA23=1
  • P5WRDATA24=1
  • P5WRDATA25=1
  • P5WRDATA26=1
  • P5WRDATA27=1
  • P5WRDATA28=1
  • P5WRDATA29=1
  • P5WRDATA3=1
  • P5WRDATA30=1
  • P5WRDATA31=1
  • P5WRDATA4=1
  • P5WRDATA5=1
  • P5WRDATA6=1
  • P5WRDATA7=1
  • P5WRDATA8=1
  • P5WRDATA9=1
  • P5WRMASK0=1
  • P5WRMASK1=1
  • P5WRMASK2=1
  • P5WRMASK3=1
  • PLLCE0=1
  • PLLCE1=1
  • PLLCLK0=1
  • PLLCLK1=1
  • PLLLOCK=1
  • RAS=1
  • RECAL=1
  • SELFREFRESHENTER=1
  • SELFREFRESHMODE=1
  • SYSRST=1
  • UDMN=1
  • UDMP=1
  • UDQSIOIN=1
  • UDQSIOIP=1
  • UIADD=1
  • UIADDR0=1
  • UIADDR1=1
  • UIADDR2=1
  • UIADDR3=1
  • UIADDR4=1
  • UIBROADCAST=1
  • UICLK=1
  • UICMD=1
  • UICMDEN=1
  • UICMDIN=1
  • UICS=1
  • UIDONECAL=1
  • UIDQCOUNT0=1
  • UIDQCOUNT1=1
  • UIDQCOUNT2=1
  • UIDQCOUNT3=1
  • UIDQLOWERDEC=1
  • UIDQLOWERINC=1
  • UIDQUPPERDEC=1
  • UIDQUPPERINC=1
  • UIDRPUPDATE=1
  • UILDQSDEC=1
  • UILDQSINC=1
  • UIREAD=1
  • UISDI=1
  • UIUDQSDEC=1
  • UIUDQSINC=1
  • UODONECAL=1
  • UOREFRSHFLAG=1
  • UOSDO=1
  • WE=1
NULLMUX
  • 0=2
  • OUT=2
OSERDES2
  • CLK0=45
  • D1=45
  • D2=45
  • D3=45
  • D4=45
  • IOCE=45
  • OCE=45
  • OQ=45
  • RST=45
  • T1=45
  • T2=45
  • T3=45
  • T4=45
  • TCE=45
  • TQ=45
  • TRAIN=45
OSERDES2_OSERDES2
  • CLK0=45
  • D1=45
  • D2=45
  • D3=45
  • D4=45
  • IOCE=45
  • OCE=45
  • OQ=45
  • RST=45
  • T1=45
  • T2=45
  • T3=45
  • T4=45
  • TCE=45
  • TQ=45
  • TRAIN=45
PAD
  • PAD=134
PLL_ADV
  • CLKFBIN=2
  • CLKFBOUT=2
  • CLKIN1=2
  • CLKOUT0=2
  • CLKOUT1=2
  • CLKOUT2=2
  • CLKOUT3=2
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • LOCKED=2
  • RST=2
PLL_ADV_PLL_ADV
  • CLKFBIN=2
  • CLKFBOUT=2
  • CLKIN1=2
  • CLKOUT0=2
  • CLKOUT1=2
  • CLKOUT2=2
  • CLKOUT3=2
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • LOCKED=2
  • RST=2
PULL_OR_KEEP1
  • PAD=39
RAMB16BWER
  • ADDRA0=22
  • ADDRA1=22
  • ADDRA10=30
  • ADDRA11=30
  • ADDRA12=30
  • ADDRA13=30
  • ADDRA2=30
  • ADDRA3=30
  • ADDRA4=30
  • ADDRA5=30
  • ADDRA6=30
  • ADDRA7=30
  • ADDRA8=30
  • ADDRA9=30
  • ADDRB0=6
  • ADDRB1=6
  • ADDRB10=14
  • ADDRB11=14
  • ADDRB12=14
  • ADDRB13=14
  • ADDRB2=14
  • ADDRB3=14
  • ADDRB4=14
  • ADDRB5=14
  • ADDRB6=14
  • ADDRB7=14
  • ADDRB8=14
  • ADDRB9=14
  • CLKA=30
  • CLKB=14
  • DIA0=30
  • DIA1=14
  • DIA10=6
  • DIA11=6
  • DIA12=6
  • DIA13=6
  • DIA14=6
  • DIA15=6
  • DIA16=6
  • DIA17=6
  • DIA18=6
  • DIA19=6
  • DIA2=14
  • DIA20=6
  • DIA21=6
  • DIA22=6
  • DIA23=6
  • DIA24=6
  • DIA25=6
  • DIA26=6
  • DIA27=6
  • DIA28=6
  • DIA29=6
  • DIA3=14
  • DIA30=6
  • DIA31=6
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=6
  • DIA9=6
  • DIB0=14
  • DIB1=14
  • DIB10=6
  • DIB11=6
  • DIB12=6
  • DIB13=6
  • DIB14=6
  • DIB15=6
  • DIB16=6
  • DIB17=6
  • DIB18=6
  • DIB19=6
  • DIB2=14
  • DIB20=6
  • DIB21=6
  • DIB22=6
  • DIB23=6
  • DIB24=6
  • DIB25=6
  • DIB26=6
  • DIB27=6
  • DIB28=6
  • DIB29=6
  • DIB3=14
  • DIB30=6
  • DIB31=6
  • DIB4=6
  • DIB5=6
  • DIB6=6
  • DIB7=6
  • DIB8=6
  • DIB9=6
  • DIPA0=6
  • DIPA1=6
  • DIPA2=6
  • DIPA3=6
  • DIPB0=6
  • DIPB1=6
  • DIPB2=6
  • DIPB3=6
  • DOA0=28
  • DOA1=12
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=2
  • DOA16=2
  • DOA17=2
  • DOA18=2
  • DOA19=2
  • DOA2=12
  • DOA20=2
  • DOA21=2
  • DOA22=2
  • DOA23=2
  • DOA24=2
  • DOA25=2
  • DOA26=2
  • DOA27=2
  • DOA28=2
  • DOA29=2
  • DOA3=11
  • DOA30=2
  • DOA31=2
  • DOA4=3
  • DOA5=3
  • DOA6=3
  • DOA7=3
  • DOA8=2
  • DOA9=2
  • DOB0=12
  • DOB1=12
  • DOB10=2
  • DOB11=2
  • DOB12=2
  • DOB13=2
  • DOB14=2
  • DOB15=2
  • DOB16=2
  • DOB17=2
  • DOB18=2
  • DOB19=2
  • DOB2=12
  • DOB20=2
  • DOB21=2
  • DOB22=2
  • DOB23=2
  • DOB24=2
  • DOB25=2
  • DOB26=2
  • DOB27=2
  • DOB28=2
  • DOB29=2
  • DOB3=12
  • DOB30=2
  • DOB31=2
  • DOB4=4
  • DOB5=4
  • DOB6=4
  • DOB7=4
  • DOB8=2
  • DOB9=2
  • DOPA0=1
  • ENA=30
  • ENB=14
  • REGCEA=6
  • REGCEB=6
  • RSTA=30
  • RSTB=14
  • WEA0=30
  • WEA1=30
  • WEA2=30
  • WEA3=30
  • WEB0=14
  • WEB1=14
  • WEB2=14
  • WEB3=14
RAMB16BWER_RAMB16BWER
  • ADDRA0=22
  • ADDRA1=22
  • ADDRA10=30
  • ADDRA11=30
  • ADDRA12=30
  • ADDRA13=30
  • ADDRA2=30
  • ADDRA3=30
  • ADDRA4=30
  • ADDRA5=30
  • ADDRA6=30
  • ADDRA7=30
  • ADDRA8=30
  • ADDRA9=30
  • ADDRB0=6
  • ADDRB1=6
  • ADDRB10=14
  • ADDRB11=14
  • ADDRB12=14
  • ADDRB13=14
  • ADDRB2=14
  • ADDRB3=14
  • ADDRB4=14
  • ADDRB5=14
  • ADDRB6=14
  • ADDRB7=14
  • ADDRB8=14
  • ADDRB9=14
  • CLKA=30
  • CLKB=14
  • DIA0=30
  • DIA1=14
  • DIA10=6
  • DIA11=6
  • DIA12=6
  • DIA13=6
  • DIA14=6
  • DIA15=6
  • DIA16=6
  • DIA17=6
  • DIA18=6
  • DIA19=6
  • DIA2=14
  • DIA20=6
  • DIA21=6
  • DIA22=6
  • DIA23=6
  • DIA24=6
  • DIA25=6
  • DIA26=6
  • DIA27=6
  • DIA28=6
  • DIA29=6
  • DIA3=14
  • DIA30=6
  • DIA31=6
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=6
  • DIA9=6
  • DIB0=14
  • DIB1=14
  • DIB10=6
  • DIB11=6
  • DIB12=6
  • DIB13=6
  • DIB14=6
  • DIB15=6
  • DIB16=6
  • DIB17=6
  • DIB18=6
  • DIB19=6
  • DIB2=14
  • DIB20=6
  • DIB21=6
  • DIB22=6
  • DIB23=6
  • DIB24=6
  • DIB25=6
  • DIB26=6
  • DIB27=6
  • DIB28=6
  • DIB29=6
  • DIB3=14
  • DIB30=6
  • DIB31=6
  • DIB4=6
  • DIB5=6
  • DIB6=6
  • DIB7=6
  • DIB8=6
  • DIB9=6
  • DIPA0=6
  • DIPA1=6
  • DIPA2=6
  • DIPA3=6
  • DIPB0=6
  • DIPB1=6
  • DIPB2=6
  • DIPB3=6
  • DOA0=28
  • DOA1=12
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=2
  • DOA16=2
  • DOA17=2
  • DOA18=2
  • DOA19=2
  • DOA2=12
  • DOA20=2
  • DOA21=2
  • DOA22=2
  • DOA23=2
  • DOA24=2
  • DOA25=2
  • DOA26=2
  • DOA27=2
  • DOA28=2
  • DOA29=2
  • DOA3=11
  • DOA30=2
  • DOA31=2
  • DOA4=3
  • DOA5=3
  • DOA6=3
  • DOA7=3
  • DOA8=2
  • DOA9=2
  • DOB0=12
  • DOB1=12
  • DOB10=2
  • DOB11=2
  • DOB12=2
  • DOB13=2
  • DOB14=2
  • DOB15=2
  • DOB16=2
  • DOB17=2
  • DOB18=2
  • DOB19=2
  • DOB2=12
  • DOB20=2
  • DOB21=2
  • DOB22=2
  • DOB23=2
  • DOB24=2
  • DOB25=2
  • DOB26=2
  • DOB27=2
  • DOB28=2
  • DOB29=2
  • DOB3=12
  • DOB30=2
  • DOB31=2
  • DOB4=4
  • DOB5=4
  • DOB6=4
  • DOB7=4
  • DOB8=2
  • DOB9=2
  • DOPA0=1
  • ENA=30
  • ENB=14
  • REGCEA=6
  • REGCEB=6
  • RSTA=30
  • RSTB=14
  • WEA0=30
  • WEA1=30
  • WEA2=30
  • WEA3=30
  • WEB0=14
  • WEB1=14
  • WEB2=14
  • WEB3=14
RAMB8BWER
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIPADIP0=2
  • DIPBDIP0=2
  • DOADO0=2
  • DOADO1=2
  • DOADO2=2
  • DOADO3=2
  • DOADO4=2
  • DOADO5=2
  • DOADO6=2
  • DOADO7=2
  • DOBDO0=2
  • DOBDO1=2
  • DOBDO2=2
  • DOBDO3=2
  • DOBDO4=2
  • DOBDO5=2
  • DOBDO6=2
  • DOBDO7=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIPADIP0=2
  • DIPBDIP0=2
  • DOADO0=2
  • DOADO1=2
  • DOADO2=2
  • DOADO3=2
  • DOADO4=2
  • DOADO5=2
  • DOADO6=2
  • DOADO7=2
  • DOBDO0=2
  • DOBDO1=2
  • DOBDO2=2
  • DOBDO3=2
  • DOBDO4=2
  • DOBDO5=2
  • DOBDO6=2
  • DOBDO7=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
REG_SR
  • CE=5006
  • CK=7363
  • D=7363
  • Q=7363
  • SR=3604
SELMUX2_1
  • 0=386
  • 1=312
  • OUT=386
  • S0=386
SLICEL
  • A=81
  • A1=176
  • A2=226
  • A3=257
  • A4=336
  • A5=359
  • A6=410
  • AMUX=110
  • AQ=186
  • AX=190
  • B=85
  • B1=169
  • B2=213
  • B3=253
  • B4=340
  • B5=358
  • B6=410
  • BMUX=185
  • BQ=186
  • BX=156
  • C=11
  • C1=203
  • C2=245
  • C3=271
  • C4=346
  • C5=362
  • C6=414
  • CE=204
  • CIN=183
  • CLK=268
  • CMUX=173
  • COUT=183
  • CQ=214
  • CX=261
  • D=21
  • D1=216
  • D2=252
  • D3=274
  • D4=343
  • D5=360
  • D6=402
  • DMUX=97
  • DQ=163
  • DX=82
  • SR=242
SLICEM
  • A=11
  • A1=49
  • A2=49
  • A3=49
  • A4=51
  • A5=58
  • A6=53
  • AI=42
  • AMUX=49
  • AQ=45
  • AX=57
  • B=9
  • B1=48
  • B2=48
  • B3=48
  • B4=49
  • B5=52
  • B6=48
  • BI=41
  • BMUX=46
  • BQ=42
  • BX=47
  • C=1
  • C1=47
  • C2=47
  • C3=47
  • C4=47
  • C5=53
  • C6=49
  • CE=48
  • CI=42
  • CIN=5
  • CLK=59
  • CMUX=37
  • COUT=5
  • CQ=41
  • CX=52
  • D=5
  • D1=54
  • D2=54
  • D3=54
  • D4=55
  • D5=58
  • D6=55
  • DI=44
  • DMUX=36
  • DQ=45
  • DX=51
  • SR=6
SLICEX
  • A=773
  • A1=916
  • A2=1424
  • A3=1645
  • A4=1713
  • A5=1863
  • A6=1716
  • AMUX=562
  • AQ=1863
  • AX=873
  • B=740
  • B1=756
  • B2=1266
  • B3=1474
  • B4=1523
  • B5=1701
  • B6=1551
  • BMUX=569
  • BQ=1610
  • BX=766
  • C=570
  • C1=645
  • C2=1099
  • C3=1323
  • C4=1364
  • C5=1517
  • C6=1360
  • CE=1328
  • CLK=2086
  • CMUX=557
  • CQ=1577
  • CX=759
  • D=590
  • D1=556
  • D2=1009
  • D3=1210
  • D4=1252
  • D5=1401
  • D6=1228
  • DMUX=565
  • DQ=1391
  • DX=738
  • SR=1106
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt on -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -detail -ir all -ignore_keep_hierarchy -pr b -lc auto -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 10 -s 2 -n 15 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -bm <fname>.bmm -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt on -ol high -xe n -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt off -detail -ir all -ignore_keep_hierarchy -pr b -lc auto -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 10 -s 2 -n 15 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 10 8 0 0 0 0 0
arwz 1 1 0 0 0 0 0
bitgen 23 23 0 0 0 0 0
map 39 30 0 0 0 0 0
ngdbuild 40 40 0 0 0 0 0
par 30 30 0 0 0 0 0
trce 30 30 0 0 0 0 0
xst 30 30 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Timing Performance
PROP_LastAppliedStrategy=Performance with Physical Synthesis;C:/Xilinx/12.3/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds PROP_LastUnlockStatus=true
PROP_ManualCompileOrderImp=false PROP_MapLUTCombining_spartan6=Auto
PROP_MapLogicOptimization_spartan6=true PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/dataBusTb PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthOptEffort_spartan6=High PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=C:/Xilinx/12.3/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_VHDLSourceAnalysisStandard=VHDL-200X PROP_intProjectCreationTimestamp=2011-02-24T19:32:37
PROP_intWbtProjectID=DD1B8F1A9C854E04B347BDEBCA743099 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_mapUseRLOCConstraints=No PROP_selectedSimRootSourceNode_behav=work.dataBusTb
PROP_xilxBitgCfg_Rate_spartan6=10 PROP_xilxBitgStart_Clk=JTAG Clock
PROP_xilxBitgStart_IntDone=true PROP_xilxMapAllowLogicOpt=true
PROP_xilxMapReportDetail=true PROP_xilxPostTrceEndpointPath=15
PROP_xilxPostTrceRptLimit=10 PROP_xilxSynthKeepHierarchy=Soft
PROP_xilxSynthRegBalancing=Yes PROP_xstAutoBRAMPacking=true
PROP_xstCrossClockAnalysis=true PROP_xstEquivRegRemoval=false
PROP_xstGenerateRTLNetlist=No PROP_xstPackIORegister=Yes
PROP_AutoTop=true PROP_CompxlibEdkSimLib=true
PROP_DevFamily=Spartan6 PROP_MapEquivalentRegisterRemoval_spartan6=false
PROP_MapExtraEffort_spartan6=Normal PROP_MapRegDuplication_spartan6=On
PROPEXT_xilxPARextraEffortLevel_spartan6=Normal PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=12 us
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_parEnableMultiThreading_spartan6=4 PROP_DevSpeed=-2
PROP_PreferredLanguage=VHDL FILE_BMM=1
FILE_COREGEN=2 FILE_UCF=1
FILE_VERILOG=38 FILE_VHDL=45
 
Core Statistics
Core Type=clk_wiz_v1_7
clkin1_period=16.0 clkin2_period=16.0 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=4 primtype_sel=PLL_BASE
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=true use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
Core Type=mig_v3_6
AXI_ENABLE=0 CLASS_ADDR=II CLASS_DATA=II CLKFBOUT_MULT_F=2
CLKOUT_DIVIDE=1 CLK_PERIOD=3200 DATA_TERMINATION=25 Ohms DEBUG_PORT=0
HIGH_TEMP_SR=NORMAL INPUT_CLK_TYPE=Single-Ended INPUT_PIN_TERMINATION=CALIB_TERM LANGUAGE=VHDL
MEMORY_PART=mt47h64m16xx-25e MEM_ADDR_ORDER=ROW_BANK_COLUMN MEM_INTERFACE_TYPE=DDR2_SDRAM NO_OF_CONTROLLERS=1
OUTPUT_DRV=FULL PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports PORT_ENABLE=Port0_Port1 RTT_NOM=50OHMS
SYNTHESIS_TOOL=ISE
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_BUFGMUX=2 XST_NUM_BUFIO2=1 XST_NUM_BUFIO2FB=1
XST_NUM_DSP48A1=1 XST_NUM_IBUFG=2 XST_NUM_IDDR2=32 XST_NUM_IOBUF=18
XST_NUM_IOBUFDS=2 XST_NUM_IODRP2=2 XST_NUM_MCB=1 XST_NUM_OBUFT=23
XST_NUM_OBUFTDS=1 XST_NUM_OSERDES2=44 XST_NUM_PULLDOWN=1 XST_NUM_PULLUP=1
XST_NUM_RAMB16BWER=6
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=8 NGDBUILD_NUM_BUFGMUX=2 NGDBUILD_NUM_BUFIO2=1 NGDBUILD_NUM_BUFIO2FB=1
NGDBUILD_NUM_BUFPLL_MCB=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_DSP48A1=3 NGDBUILD_NUM_FD=1913
NGDBUILD_NUM_FDC=575 NGDBUILD_NUM_FDCE=1558 NGDBUILD_NUM_FDE=2993 NGDBUILD_NUM_FDP=125
NGDBUILD_NUM_FDPE=50 NGDBUILD_NUM_FDR=392 NGDBUILD_NUM_FDRE=1442 NGDBUILD_NUM_FDS=22
NGDBUILD_NUM_FDSE=16 NGDBUILD_NUM_GND=41 NGDBUILD_NUM_IBUF=52 NGDBUILD_NUM_IBUFG=2
NGDBUILD_NUM_IDDR2=32 NGDBUILD_NUM_INV=144 NGDBUILD_NUM_IOBUF=19 NGDBUILD_NUM_IOBUFDS=2
NGDBUILD_NUM_IODRP2=2 NGDBUILD_NUM_IODRP2_MCB=22 NGDBUILD_NUM_LUT1=352 NGDBUILD_NUM_LUT2=505
NGDBUILD_NUM_LUT3=2434 NGDBUILD_NUM_LUT4=1384 NGDBUILD_NUM_LUT5=1523 NGDBUILD_NUM_LUT6=2942
NGDBUILD_NUM_MCB=1 NGDBUILD_NUM_MULT_AND=6 NGDBUILD_NUM_MUXCY=940 NGDBUILD_NUM_MUXF7=245
NGDBUILD_NUM_MUXF8=67 NGDBUILD_NUM_OBUF=27 NGDBUILD_NUM_OBUFT=23 NGDBUILD_NUM_OBUFTDS=1
NGDBUILD_NUM_OSERDES2=44 NGDBUILD_NUM_PLL_ADV=1 NGDBUILD_NUM_PULLDOWN=2 NGDBUILD_NUM_PULLUP=2
NGDBUILD_NUM_RAM16X1D=32 NGDBUILD_NUM_RAMB16BWER=30 NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_SRLC16E=268
NGDBUILD_NUM_VCC=39 NGDBUILD_NUM_XORCY=830
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=8 NGDBUILD_NUM_BUFGMUX=2 NGDBUILD_NUM_BUFIO2=1 NGDBUILD_NUM_BUFIO2FB=1
NGDBUILD_NUM_BUFPLL_MCB=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_DSP48A1=3 NGDBUILD_NUM_FD=1913
NGDBUILD_NUM_FDC=575 NGDBUILD_NUM_FDCE=1558 NGDBUILD_NUM_FDE=2993 NGDBUILD_NUM_FDP=125
NGDBUILD_NUM_FDPE=50 NGDBUILD_NUM_FDR=392 NGDBUILD_NUM_FDRE=1442 NGDBUILD_NUM_FDS=22
NGDBUILD_NUM_FDSE=16 NGDBUILD_NUM_GND=41 NGDBUILD_NUM_IBUF=76 NGDBUILD_NUM_IBUFDS=2
NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_IDDR2=32 NGDBUILD_NUM_INV=144 NGDBUILD_NUM_IODRP2=2
NGDBUILD_NUM_IODRP2_MCB=22 NGDBUILD_NUM_LUT1=352 NGDBUILD_NUM_LUT2=505 NGDBUILD_NUM_LUT3=2434
NGDBUILD_NUM_LUT4=1384 NGDBUILD_NUM_LUT5=1523 NGDBUILD_NUM_LUT6=2942 NGDBUILD_NUM_MCB=1
NGDBUILD_NUM_MULT_AND=6 NGDBUILD_NUM_MUXCY=940 NGDBUILD_NUM_MUXF7=245 NGDBUILD_NUM_MUXF8=67
NGDBUILD_NUM_OBUF=27 NGDBUILD_NUM_OBUFT=42 NGDBUILD_NUM_OBUFTDS=3 NGDBUILD_NUM_OSERDES2=44
NGDBUILD_NUM_PLL_ADV=2 NGDBUILD_NUM_PULLDOWN=35 NGDBUILD_NUM_PULLUP=4 NGDBUILD_NUM_RAMB16BWER=30
NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_SRLC16E=268 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=39
NGDBUILD_NUM_XORCY=830
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx45-2-csg324
-top=<design_top> -opt_mode=Speed -opt_level=2 -power=NO
-iuc=NO -keep_hierarchy=Soft -netlist_hierarchy=As_Optimized -rtlview=No
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=YES -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=YES
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=Yes
-move_first_stage=YES -move_last_stage=YES -optimize_primitives=NO -use_clock_enable=Auto
-use_sync_set=Auto -use_sync_reset=Auto -iob=True -equivalent_register_removal=NO
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee, unisim, vl, std
Fuse Resource Usage=5570 ms, 813268 KB
Total Signals=4904
Total Nets=31318
Total Blocks=498
Total Processes=2301
Total Simulation Time=12 us
Simulation Resource Usage=0.83 sec, 295378 KB
Simulation Mode=gui
Hardware CoSim=0