LATop Project Status (01/09/2013 - 20:11:50)
Project File: BitHoundDigilent.xise Parser Errors: No Errors
Module Name: LATop Implementation State: Programming File Generated
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
733 Warnings (1 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: Performance with Physical Synthesis (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 9,064 54,576 16%  
    Number used as Flip Flops 9,051      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 13      
Number of Slice LUTs 8,392 27,288 30%  
    Number used as logic 7,599 27,288 27%  
        Number using O6 output only 5,310      
        Number using O5 output only 374      
        Number using O5 and O6 1,915      
        Number used as ROM 0      
    Number used as Memory 169 6,408 2%  
        Number used as Dual Port RAM 32      
            Number using O6 output only 0      
            Number using O5 output only 0      
            Number using O5 and O6 32      
        Number used as Single Port RAM 0      
        Number used as Shift Register 137      
            Number using O6 output only 6      
            Number using O5 output only 0      
            Number using O5 and O6 131      
    Number used exclusively as route-thrus 624      
        Number with same-slice register load 604      
        Number with same-slice carry load 20      
        Number with other load 0      
Number of occupied Slices 2,820 6,822 41%  
Number of MUXCYs used 1,088 13,644 7%  
Number of LUT Flip Flop pairs used 10,007      
    Number with an unused Flip Flop 2,573 10,007 25%  
    Number with an unused LUT 1,615 10,007 16%  
    Number of fully used LUT-FF pairs 5,819 10,007 58%  
    Number of unique control sets 361      
    Number of slice register sites lost
        to control set restrictions
753 54,576 1%  
Number of bonded IOBs 134 218 61%  
    Number of LOCed IOBs 134 134 100%  
    IOB Flip Flops 42      
Number of RAMB16BWERs 30 116 25%  
Number of RAMB8BWERs 2 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 10 16 62%  
    Number used as BUFGs 8      
    Number used as BUFGMUX 2      
Number of DCM/DCM_CLKGENs 1 8 12%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 42 376 11%  
    Number used as ILOGIC2s 42      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 24 376 6%  
    Number used as IODELAY2s 0      
    Number used as IODRP2s 2      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 45 376 11%  
    Number used as OLOGIC2s 0      
    Number used as OSERDES2s 45      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 3 58 5%  
    Number of LOCed DSP48A1s 2 3 66%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 2 4 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.69      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 9 19:57:34 20130663 Warnings (0 new)345 Infos (68 new)
Translation ReportCurrentTue Apr 9 19:57:53 2013059 Warnings (1 new)11 Infos (0 new)
Map ReportCurrentTue Apr 9 20:06:51 201301 Warning (0 new)223 Infos (0 new)
Place and Route ReportCurrentTue Apr 9 20:09:01 201309 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Apr 9 20:09:38 2013004 Infos (0 new)
Bitgen ReportCurrentTue Apr 9 20:42:00 201301 Warning (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon Apr 8 21:12:56 2013
Post-Synthesis Simulation Model ReportOut of DateSat Oct 27 16:16:59 2012
Physical Synthesis ReportCurrentTue Apr 9 20:06:51 2013
WebTalk ReportCurrentTue Apr 9 20:42:05 2013
WebTalk Log FileCurrentTue Apr 9 20:42:06 2013

Date Generated: 04/14/2013 - 21:10:49