Project Statistics |
PROPEXT_MapGlobalOptimization_spartan6=Speed |
PROPEXT_xilxMapPackRegInto_spartan6=For Inputs and Outputs |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Timing Performance |
PROP_LastAppliedStrategy=Performance with Physical Synthesis;C:/Xilinx/12.3/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds |
PROP_LastUnlockStatus=true |
PROP_ManualCompileOrderImp=false |
PROP_MapLUTCombining_spartan6=Auto |
PROP_MapLogicOptimization_spartan6=true |
PROP_MapRegDuplication_spartan6=On |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/SamplingCore_TB |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOptEffort_spartan6=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/12.3/ISE_DS/ISE/spartan6/data/spartan6_performance_with_physicalsynthesis.xds |
PROP_UserConstraintEditorPreference=Constraints Editor |
PROP_intProjectCreationTimestamp=2011-02-24T19:32:37 |
PROP_intWbtProjectID=DD1B8F1A9C854E04B347BDEBCA743099 |
PROP_intWbtProjectIteration=24 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_mapUseRLOCConstraints=No |
PROP_selectedSimRootSourceNode_behav=work.SamplingCore_TB |
PROP_xilxBitgCfg_Rate_spartan6=10 |
PROP_xilxBitgStart_Clk=JTAG Clock |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxMapAllowLogicOpt=true |
PROP_xilxMapReportDetail=true |
PROP_xilxPostTrceEndpointPath=15 |
PROP_xilxPostTrceRptLimit=10 |
PROP_xilxSynthKeepHierarchy=Soft |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstAutoBRAMPacking=true |
PROP_xstCrossClockAnalysis=true |
PROP_xstEquivRegRemoval=false |
PROP_xstPackIORegister=Yes |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_MapEquivalentRegisterRemoval_spartan6=false |
PROP_MapExtraEffort_spartan6=Normal |
PROP_MapRetiming_spartan6=true |
PROPEXT_xilxPARextraEffortLevel_spartan6=Normal |
PROP_DevDevice=xc6slx45 |
PROP_DevFamilyPMName=spartan6 |
PROP_ISimSimulationRunTime_behav_tb=12 us |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_parEnableMultiThreading_spartan6=4 |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=VHDL |
FILE_BMM=1 |
FILE_COREGEN=2 |
FILE_UCF=1 |
FILE_VERILOG=37 |
FILE_VHDL=39 |